hw/block/nvme: change controller pci id
There are two reasons for changing this:
1. The nvme device currently uses an internal Intel device id.
2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
support multiple namespaces" the controller device no longer has
the quirks that the Linux kernel think it has.
As the quirks are applied based on pci vendor and device id, change
them to get rid of the quirks.
To keep backward compatibility, add a new 'use-intel-id' parameter to
the nvme device to force use of the Intel vendor and device id. This is
off by default but add a compat property to set this for 5.1 machines
and older. If a 5.1 machine is booted (or the use-intel-id parameter is
explicitly set to true), the Linux kernel will just apply these
unnecessary quirks:
1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
anything else than values 0x0 and 0x1 for CNS (Identify Namespace
and Identify Namespace). With multiple namespace support, this just
means that the kernel will "scan" namespaces instead of using
"Active Namespace ID list" (CNS 0x2).
2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
broken Write Zeroes implementation which has since been fixed in
commit 9d6459d21a
("nvme: fix write zeroes offset and count").
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
This commit is contained in:
parent
c1e1824661
commit
6eb7a07129
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@ -2678,6 +2678,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
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pci_conf[PCI_INTERRUPT_PIN] = 1;
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pci_conf[PCI_INTERRUPT_PIN] = 1;
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pci_config_set_prog_interface(pci_conf, 0x2);
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pci_config_set_prog_interface(pci_conf, 0x2);
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if (n->params.use_intel_id) {
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(pci_conf, 0x5845);
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} else {
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
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}
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pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
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pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
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pcie_endpoint_cap_init(pci_dev, 0x80);
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pcie_endpoint_cap_init(pci_dev, 0x80);
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@ -2831,6 +2840,7 @@ static Property nvme_props[] = {
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DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
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DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
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DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
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DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
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DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
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DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
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DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -2847,8 +2857,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
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pc->realize = nvme_realize;
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pc->realize = nvme_realize;
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pc->exit = nvme_exit;
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pc->exit = nvme_exit;
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pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
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pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
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pc->vendor_id = PCI_VENDOR_ID_INTEL;
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pc->device_id = 0x5845;
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pc->revision = 2;
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pc->revision = 2;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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@ -15,6 +15,7 @@ typedef struct NvmeParams {
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uint8_t aerl;
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uint8_t aerl;
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uint32_t aer_max_queued;
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uint32_t aer_max_queued;
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uint8_t mdts;
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uint8_t mdts;
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bool use_intel_id;
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} NvmeParams;
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} NvmeParams;
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typedef struct NvmeAsyncEvent {
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typedef struct NvmeAsyncEvent {
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@ -34,6 +34,7 @@ GlobalProperty hw_compat_5_1[] = {
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{ "vhost-user-scsi", "num_queues", "1"},
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{ "vhost-user-scsi", "num_queues", "1"},
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{ "virtio-blk-device", "num-queues", "1"},
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{ "virtio-blk-device", "num-queues", "1"},
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{ "virtio-scsi-device", "num_queues", "1"},
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{ "virtio-scsi-device", "num_queues", "1"},
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{ "nvme", "use-intel-id", "on"},
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};
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};
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const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
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const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
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