target/arm: Convert double-single precision conversion insns to decodetree
Convert the VCVT double/single precision conversion insns to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -2320,3 +2320,51 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
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tcg_temp_free_i64(tmp);
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return true;
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}
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static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
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{
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TCGv_i64 vd;
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TCGv_i32 vm;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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vm = tcg_temp_new_i32();
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vd = tcg_temp_new_i64();
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neon_load_reg32(vm, a->vm);
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gen_helper_vfp_fcvtds(vd, vm, cpu_env);
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neon_store_reg64(vd, a->vd);
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tcg_temp_free_i32(vm);
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tcg_temp_free_i64(vd);
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return true;
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}
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static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
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{
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TCGv_i64 vm;
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TCGv_i32 vd;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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vd = tcg_temp_new_i32();
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vm = tcg_temp_new_i64();
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neon_load_reg64(vm, a->vm);
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gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
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neon_store_reg32(vd, a->vd);
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tcg_temp_free_i32(vd);
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tcg_temp_free_i64(vm);
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return true;
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}
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@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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return 1;
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case 15:
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switch (rn) {
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case 0 ... 14:
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case 0 ... 15:
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/* Already handled by decodetree */
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return 1;
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default:
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@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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if (op == 15) {
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x0f: /* vcvt double<->single */
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rd_is_dp = !dp;
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break;
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case 0x10: /* vcvt.fxx.u32 */
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case 0x11: /* vcvt.fxx.s32 */
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rm_is_dp = false;
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@ -3185,13 +3181,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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switch (op) {
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case 15: /* extension space */
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switch (rn) {
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case 15: /* single<->double conversion */
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if (dp) {
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gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
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} else {
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gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
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}
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break;
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case 16: /* fuito */
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gen_vfp_uito(dp, 0);
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break;
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@ -208,3 +208,9 @@ VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
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vd=%vd_sp vm=%vm_sp
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VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
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vd=%vd_dp vm=%vm_dp
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# VCVT between single and double: Vm precision depends on size; Vd is its reverse
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VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
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vd=%vd_dp vm=%vm_sp
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VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
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vd=%vd_sp vm=%vm_dp
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