target/arm: Perform fpdp_v2 check first
Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7d63183ff1
commit
799449abda
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@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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return false;
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}
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@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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return false;
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}
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@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vd) & 0x10)) {
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vd) & 0x10)) {
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return false;
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}
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@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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return false;
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}
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@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
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TCGv_i64 f0, f1, fd;
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TCGv_ptr fpst;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
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return false;
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}
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@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
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int veclen = s->vec_len;
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TCGv_i64 f0, fd;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
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return false;
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}
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@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
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vd = a->vd;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
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return false;
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}
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@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
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{
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TCGv_i64 vd, vm;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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/* Vm/M bits must be zero for the Z variant */
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if (a->z && a->vm != 0) {
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return false;
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@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
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TCGv_i32 tmp;
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TCGv_i64 vd;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
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return false;
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}
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@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
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TCGv_i32 tmp;
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TCGv_i64 vm;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
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return false;
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}
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@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
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TCGv_ptr fpst;
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TCGv_i64 tmp;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
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TCGv_i64 tmp;
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TCGv_i32 tcg_rmode;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
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TCGv_ptr fpst;
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TCGv_i64 tmp;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_vrint, s)) {
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return false;
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}
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@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
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TCGv_i64 vd;
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TCGv_i32 vm;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
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return false;
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}
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@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
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TCGv_i64 vm;
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TCGv_i32 vd;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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return false;
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}
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@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
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TCGv_i64 vd;
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TCGv_ptr fpst;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
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return false;
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}
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@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
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TCGv_i32 vd;
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TCGv_i64 vm;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_jscvt, s)) {
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return false;
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}
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@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
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TCGv_ptr fpst;
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int frac_bits;
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return false;
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}
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@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
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TCGv_i64 vm;
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TCGv_ptr fpst;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpdp_v2, s)) {
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
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return false;
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}
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