ahci: split ICH and AHCI even more
Sebastian's patch already did a pretty good job at splitting up ICH-9 AHCI code and the AHCI core. We need some more though. Copyright was missing, the lspci dump belongs to ICH-9, we don't need the AHCI core to have its own qdev device duplicate. So let's split them a bit more in this patch, making things easier to read an understand. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
This commit is contained in:
Alexander Graf
Kevin Wolf
parent
f83a40dcd7
commit
7fb6577b13
110
hw/ide/ahci.c
110
hw/ide/ahci.c
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@ -19,47 +19,6 @@
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* lspci dump of a ICH-9 real device in IDE mode (hopefully close enough):
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*
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* 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
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* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
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* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
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* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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* Latency: 0
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* Interrupt: pin B routed to IRQ 222
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* Region 0: I/O ports at d000 [size=8]
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* Region 1: I/O ports at cc00 [size=4]
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* Region 2: I/O ports at c880 [size=8]
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* Region 3: I/O ports at c800 [size=4]
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* Region 4: I/O ports at c480 [size=32]
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* Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
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* Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
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* Address: fee0f00c Data: 41d9
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* Capabilities: [70] Power Management version 3
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* Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
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* Status: D0 PME-Enable- DSel=0 DScale=0 PME-
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* Capabilities: [a8] SATA HBA <?>
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* Capabilities: [b0] Vendor Specific Information <?>
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* Kernel driver in use: ahci
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* Kernel modules: ahci
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* 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
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* 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
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* 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
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* 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
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* 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
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* 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
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* 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
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* 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
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* a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
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* b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
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* c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
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*
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*/
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#include <hw/hw.h>
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@ -1155,72 +1114,3 @@ void ahci_reset(void *opaque)
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ahci_reset_port(&d->ahci, i);
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}
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}
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static int pci_ahci_init(PCIDevice *dev)
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{
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struct AHCIPCIState *d;
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d = DO_UPCAST(struct AHCIPCIState, card, dev);
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pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
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pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
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pci_config_set_revision(d->card.config, 0x02);
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pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
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d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
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d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
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pci_config_set_interrupt_pin(d->card.config, 1);
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/* XXX Software should program this register */
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d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
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qemu_register_reset(ahci_reset, d);
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/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
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pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY,
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ahci_pci_map);
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msi_init(dev, 0x50, 1, true, false);
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ahci_init(&d->ahci, &dev->qdev);
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d->ahci.irq = d->card.irq[0];
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return 0;
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}
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static int pci_ahci_uninit(PCIDevice *dev)
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{
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struct AHCIPCIState *d;
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d = DO_UPCAST(struct AHCIPCIState, card, dev);
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if (msi_enabled(dev)) {
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msi_uninit(dev);
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}
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qemu_unregister_reset(ahci_reset, d);
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return 0;
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}
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static void pci_ahci_write_config(PCIDevice *pci, uint32_t addr,
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uint32_t val, int len)
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{
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pci_default_write_config(pci, addr, val, len);
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msi_write_config(pci, addr, val, len);
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}
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static PCIDeviceInfo ahci_info = {
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.qdev.name = "ahci",
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.qdev.size = sizeof(AHCIPCIState),
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.init = pci_ahci_init,
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.exit = pci_ahci_uninit,
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.config_write = pci_ahci_write_config,
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};
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static void ahci_pci_register_devices(void)
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{
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pci_qdev_register(&ahci_info);
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}
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device_init(ahci_pci_register_devices)
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90
hw/ide/ich.c
90
hw/ide/ich.c
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@ -1,3 +1,65 @@
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/*
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* QEMU ICH Emulation
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*
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* Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
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* Copyright (c) 2010 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* lspci dump of a ICH-9 real device
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*
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* 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
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* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
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* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
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* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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* Latency: 0
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* Interrupt: pin B routed to IRQ 222
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* Region 0: I/O ports at d000 [size=8]
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* Region 1: I/O ports at cc00 [size=4]
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* Region 2: I/O ports at c880 [size=8]
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* Region 3: I/O ports at c800 [size=4]
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* Region 4: I/O ports at c480 [size=32]
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* Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
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* Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
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* Address: fee0f00c Data: 41d9
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* Capabilities: [70] Power Management version 3
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* Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
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* Status: D0 PME-Enable- DSel=0 DScale=0 PME-
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* Capabilities: [a8] SATA HBA <?>
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* Capabilities: [b0] Vendor Specific Information <?>
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* Kernel driver in use: ahci
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* Kernel modules: ahci
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* 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
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* 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
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* 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
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* 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
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* 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
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* 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
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* 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
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* 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
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* a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
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* b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
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* c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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* f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
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*
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*/
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#include <hw/hw.h>
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#include <hw/msi.h>
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#include <hw/pc.h>
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@ -11,7 +73,7 @@
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#include <hw/ide/pci.h>
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#include <hw/ide/ahci.h>
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static int pci_ich9_ahci_initfn(PCIDevice *dev)
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static int pci_ich9_ahci_init(PCIDevice *dev)
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{
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struct AHCIPCIState *d;
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d = DO_UPCAST(struct AHCIPCIState, card, dev);
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@ -44,11 +106,35 @@ static int pci_ich9_ahci_initfn(PCIDevice *dev)
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return 0;
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}
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static int pci_ich9_uninit(PCIDevice *dev)
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{
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struct AHCIPCIState *d;
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d = DO_UPCAST(struct AHCIPCIState, card, dev);
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if (msi_enabled(dev)) {
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msi_uninit(dev);
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}
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qemu_unregister_reset(ahci_reset, d);
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return 0;
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}
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static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr,
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uint32_t val, int len)
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{
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pci_default_write_config(pci, addr, val, len);
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msi_write_config(pci, addr, val, len);
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}
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static PCIDeviceInfo ich_ahci_info[] = {
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{
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.qdev.name = "ich9-ahci",
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.qdev.alias = "ahci",
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.qdev.size = sizeof(AHCIPCIState),
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.init = pci_ich9_ahci_initfn,
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.init = pci_ich9_ahci_init,
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.exit = pci_ich9_uninit,
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.config_write = pci_ich9_write_config,
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},{
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/* end of list */
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}
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