ahci: send init d2h fis on fis enable
The drive sends a d2h init fis on initialization. Usually, the guest doesn't receive fises yet at that point though, so the delivery is deferred. Let's reflect that by sending the init fis on fis receive enablement. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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@ -47,6 +47,7 @@ static void check_cmd(AHCIState *s, int port);
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static int handle_cmd(AHCIState *s,int port,int slot);
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static int handle_cmd(AHCIState *s,int port,int slot);
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static void ahci_reset_port(AHCIState *s, int port);
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static void ahci_reset_port(AHCIState *s, int port);
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static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
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static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
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static void ahci_init_d2h(AHCIDevice *ad);
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static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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{
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{
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@ -230,6 +231,16 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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pr->cmd |= PORT_CMD_FIS_ON;
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pr->cmd |= PORT_CMD_FIS_ON;
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}
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}
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/* XXX usually the FIS would be pending on the bus here and
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issuing deferred until the OS enables FIS receival.
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Instead, we only submit it once - which works in most
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cases, but is a hack. */
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if ((pr->cmd & PORT_CMD_FIS_ON) &&
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!s->dev[port].init_d2h_sent) {
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ahci_init_d2h(&s->dev[port]);
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s->dev[port].init_d2h_sent = 1;
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}
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check_cmd(s, port);
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check_cmd(s, port);
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break;
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break;
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case PORT_TFDATA:
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case PORT_TFDATA:
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@ -462,12 +473,29 @@ static void ahci_check_cmd_bh(void *opaque)
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check_cmd(ad->hba, ad->port_no);
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check_cmd(ad->hba, ad->port_no);
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}
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}
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static void ahci_init_d2h(AHCIDevice *ad)
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{
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uint8_t init_fis[0x20];
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IDEState *ide_state = &ad->port.ifs[0];
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memset(init_fis, 0, sizeof(init_fis));
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init_fis[4] = 1;
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init_fis[12] = 1;
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if (ide_state->drive_kind == IDE_CD) {
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init_fis[5] = ide_state->lcyl;
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init_fis[6] = ide_state->hcyl;
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}
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ahci_write_fis_d2h(ad, init_fis);
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}
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static void ahci_reset_port(AHCIState *s, int port)
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static void ahci_reset_port(AHCIState *s, int port)
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{
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{
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AHCIDevice *d = &s->dev[port];
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AHCIDevice *d = &s->dev[port];
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AHCIPortRegs *pr = &d->port_regs;
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AHCIPortRegs *pr = &d->port_regs;
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IDEState *ide_state = &d->port.ifs[0];
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IDEState *ide_state = &d->port.ifs[0];
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uint8_t init_fis[0x20];
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int i;
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int i;
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DPRINTF(port, "reset port\n");
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DPRINTF(port, "reset port\n");
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@ -482,6 +510,7 @@ static void ahci_reset_port(AHCIState *s, int port)
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pr->scr_err = 0;
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pr->scr_err = 0;
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pr->scr_act = 0;
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pr->scr_act = 0;
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d->busy_slot = -1;
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d->busy_slot = -1;
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d->init_d2h_sent = 0;
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ide_state = &s->dev[port].port.ifs[0];
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ide_state = &s->dev[port].port.ifs[0];
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if (!ide_state->bs) {
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if (!ide_state->bs) {
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@ -504,7 +533,6 @@ static void ahci_reset_port(AHCIState *s, int port)
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ncq_tfs->used = 0;
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ncq_tfs->used = 0;
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}
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}
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memset(init_fis, 0, sizeof(init_fis));
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s->dev[port].port_state = STATE_RUN;
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s->dev[port].port_state = STATE_RUN;
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if (!ide_state->bs) {
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if (!ide_state->bs) {
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s->dev[port].port_regs.sig = 0;
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s->dev[port].port_regs.sig = 0;
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@ -514,8 +542,6 @@ static void ahci_reset_port(AHCIState *s, int port)
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ide_state->lcyl = 0x14;
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ide_state->lcyl = 0x14;
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ide_state->hcyl = 0xeb;
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ide_state->hcyl = 0xeb;
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DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
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DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
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init_fis[5] = ide_state->lcyl;
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init_fis[6] = ide_state->hcyl;
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ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
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ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
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} else {
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} else {
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s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK;
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s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK;
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@ -523,9 +549,7 @@ static void ahci_reset_port(AHCIState *s, int port)
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}
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}
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ide_state->error = 1;
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ide_state->error = 1;
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init_fis[4] = 1;
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ahci_init_d2h(d);
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init_fis[12] = 1;
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ahci_write_fis_d2h(d, init_fis);
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}
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}
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static void debug_print_fis(uint8_t *fis, int cmd_len)
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static void debug_print_fis(uint8_t *fis, int cmd_len)
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@ -282,6 +282,7 @@ struct AHCIDevice {
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int dma_status;
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int dma_status;
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int done_atapi_packet;
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int done_atapi_packet;
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int busy_slot;
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int busy_slot;
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int init_d2h_sent;
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BlockDriverCompletionFunc *dma_cb;
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BlockDriverCompletionFunc *dma_cb;
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AHCICmdHdr *cur_cmd;
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AHCICmdHdr *cur_cmd;
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NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
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NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
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