target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj)
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
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/*
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* Begin with full support for MTE. This will be downgraded to MTE=0
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* during realize if the board provides no tag memory, much like
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@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj)
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u = FIELD_DP32(u, ID_PFR0, DIT, 1);
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cpu->isar.id_pfr0 = u;
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u = cpu->isar.id_pfr2;
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u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
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cpu->isar.id_pfr2 = u;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->isar.id_mmfr3 = u;
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