hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -53,7 +53,7 @@ static const struct MemmapEntry {
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[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
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};
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static void riscv_opentitan_init(MachineState *machine)
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static void opentitan_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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OpenTitanState *s = g_new0(OpenTitanState, 1);
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@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
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memory_region_add_subregion(sys_mem,
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memmap[IBEX_RAM].base, main_mem);
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if (machine->firmware) {
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riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
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}
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@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
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}
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}
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static void riscv_opentitan_machine_init(MachineClass *mc)
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static void opentitan_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with OpenTitan";
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mc->init = riscv_opentitan_init;
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mc->init = opentitan_board_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
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}
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DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
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DEFINE_MACHINE("opentitan", opentitan_machine_init)
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static void riscv_lowrisc_ibex_soc_init(Object *obj)
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static void lowrisc_ibex_soc_init(Object *obj)
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{
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LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
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@ -101,7 +100,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
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object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
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}
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static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
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static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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MachineState *ms = MACHINE(qdev_get_machine());
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@ -186,26 +185,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
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memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
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}
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static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
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static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = riscv_lowrisc_ibex_soc_realize;
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dc->realize = lowrisc_ibex_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
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static const TypeInfo lowrisc_ibex_soc_type_info = {
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.name = TYPE_RISCV_IBEX_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(LowRISCIbexSoCState),
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.instance_init = riscv_lowrisc_ibex_soc_init,
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.class_init = riscv_lowrisc_ibex_soc_class_init,
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.instance_init = lowrisc_ibex_soc_init,
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.class_init = lowrisc_ibex_soc_class_init,
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};
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static void riscv_lowrisc_ibex_soc_register_types(void)
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static void lowrisc_ibex_soc_register_types(void)
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{
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type_register_static(&riscv_lowrisc_ibex_soc_type_info);
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type_register_static(&lowrisc_ibex_soc_type_info);
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}
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type_init(riscv_lowrisc_ibex_soc_register_types)
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type_init(lowrisc_ibex_soc_register_types)
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