target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters sub-struct. We're going to want id_pfr1 for an isar_features check, and moving both at the same time avoids an odd inconsistency. Changes other than the ones to cpu.h and kvm64.c made automatically with: perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
0ae0326b98
commit
8a130a7be6
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@ -1238,9 +1238,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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"Aux Fault status registers unimplemented\n");
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return 0;
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case 0xd40: /* PFR0. */
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return cpu->id_pfr0;
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return cpu->isar.id_pfr0;
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case 0xd44: /* PFR1. */
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return cpu->id_pfr1;
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return cpu->isar.id_pfr1;
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case 0xd48: /* DFR0. */
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return cpu->isar.id_dfr0;
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case 0xd4c: /* AFR0. */
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@ -1659,7 +1659,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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/* Disable the security extension feature bits in the processor feature
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* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
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*/
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cpu->id_pfr1 &= ~0xf0;
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cpu->isar.id_pfr1 &= ~0xf0;
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cpu->isar.id_aa64pfr0 &= ~0xf000;
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}
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@ -1696,7 +1696,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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* id_aa64pfr0_el1[11:8].
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*/
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cpu->isar.id_aa64pfr0 &= ~0xf00;
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cpu->id_pfr1 &= ~0xf000;
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cpu->isar.id_pfr1 &= ~0xf000;
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}
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#ifndef CONFIG_USER_ONLY
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@ -1894,8 +1894,8 @@ static void cortex_a8_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x00011111;
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cpu->ctr = 0x82048004;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_pfr0 = 0x1031;
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cpu->isar.id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x400;
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cpu->id_afr0 = 0;
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cpu->isar.id_mmfr0 = 0x31100003;
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@ -1966,8 +1966,8 @@ static void cortex_a9_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x01111111;
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cpu->ctr = 0x80038003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_pfr0 = 0x1031;
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cpu->isar.id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x000;
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cpu->id_afr0 = 0;
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cpu->isar.id_mmfr0 = 0x00100103;
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@ -2030,8 +2030,8 @@ static void cortex_a7_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x11111111;
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cpu->ctr = 0x84448003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_pfr0 = 0x00001131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10101105;
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@ -2075,8 +2075,8 @@ static void cortex_a15_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x11111111;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_pfr0 = 0x00001131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10201105;
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@ -906,6 +906,8 @@ struct ARMCPU {
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t mvfr2;
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@ -926,8 +928,6 @@ struct ARMCPU {
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uint32_t reset_fpsid;
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uint32_t ctr;
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uint32_t reset_sctlr;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint64_t pmceid0;
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uint64_t pmceid1;
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uint32_t id_afr0;
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@ -108,8 +108,8 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10101105;
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@ -161,8 +161,8 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10101105;
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@ -213,8 +213,8 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_pfr0 = 0x00000131;
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cpu->isar.id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x10201105;
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@ -142,8 +142,8 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_pfr0 = 0x111;
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cpu->isar.id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->isar.id_mmfr0 = 0x01130003;
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@ -173,8 +173,8 @@ static void arm1136_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_pfr0 = 0x111;
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cpu->isar.id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->isar.id_mmfr0 = 0x01130003;
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@ -205,8 +205,8 @@ static void arm1176_initfn(Object *obj)
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_pfr0 = 0x111;
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cpu->isar.id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->isar.id_mmfr0 = 0x01130003;
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@ -234,8 +234,8 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_pfr0 = 0x111;
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cpu->isar.id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->isar.id_mmfr0 = 0x01100103;
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@ -266,8 +266,8 @@ static void cortex_m3_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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cpu->midr = 0x410fc231;
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cpu->pmsav7_dregion = 8;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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@ -296,8 +296,8 @@ static void cortex_m4_initfn(Object *obj)
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cpu->isar.mvfr0 = 0x10110021;
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cpu->isar.mvfr1 = 0x11000011;
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cpu->isar.mvfr2 = 0x00000000;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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@ -326,8 +326,8 @@ static void cortex_m7_initfn(Object *obj)
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cpu->isar.mvfr0 = 0x10110221;
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cpu->isar.mvfr1 = 0x12000011;
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cpu->isar.mvfr2 = 0x00000040;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00100030;
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@ -358,8 +358,8 @@ static void cortex_m33_initfn(Object *obj)
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cpu->isar.mvfr0 = 0x10110021;
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cpu->isar.mvfr1 = 0x11000011;
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cpu->isar.mvfr2 = 0x00000040;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000210;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000210;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00101F40;
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@ -397,8 +397,8 @@ static void cortex_r5_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_PMSA);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->midr = 0x411fc153; /* r1p3 */
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cpu->id_pfr0 = 0x0131;
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cpu->id_pfr1 = 0x001;
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cpu->isar.id_pfr0 = 0x0131;
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cpu->isar.id_pfr1 = 0x001;
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cpu->isar.id_dfr0 = 0x010400;
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cpu->id_afr0 = 0x0;
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cpu->isar.id_mmfr0 = 0x0210030;
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@ -6625,7 +6625,7 @@ static void define_pmu_regs(ARMCPU *cpu)
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static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = env_archcpu(env);
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uint64_t pfr1 = cpu->id_pfr1;
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uint64_t pfr1 = cpu->isar.id_pfr1;
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if (env->gicv3state) {
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pfr1 |= 1 << 28;
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@ -7258,7 +7258,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_pfr0 },
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.resetvalue = cpu->isar.id_pfr0 },
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/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
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* the value of the GIC field until after we define these regs.
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*/
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@ -555,6 +555,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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* than skipping the reads and leaving 0, as we must avoid
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* considering the values in every case.
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*/
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
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ARM64_SYS_REG(3, 0, 0, 1, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
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