target/arm: Convert VABS to decodetree
Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1111,6 +1111,14 @@ typedef void VFPGen3OpSPFn(TCGv_i32 vd,
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typedef void VFPGen3OpDPFn(TCGv_i64 vd,
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TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst);
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/*
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* Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
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* The callback should emit code to write a value to vd (which
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* should be written to only).
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*/
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typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm);
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typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm);
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/*
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* Perform a 3-operand VFP data processing instruction. fn is the
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* callback to do the actual operation; this function deals with the
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@ -1274,6 +1282,155 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
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return true;
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}
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static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
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{
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uint32_t delta_m = 0;
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uint32_t delta_d = 0;
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uint32_t bank_mask = 0;
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int veclen = s->vec_len;
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TCGv_i32 f0, fd;
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if (!dc_isar_feature(aa32_fpshvec, s) &&
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(veclen != 0 || s->vec_stride != 0)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (veclen > 0) {
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bank_mask = 0x18;
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/* Figure out what type of vector operation this is. */
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if ((vd & bank_mask) == 0) {
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/* scalar */
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veclen = 0;
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} else {
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delta_d = s->vec_stride + 1;
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if ((vm & bank_mask) == 0) {
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/* mixed scalar/vector */
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delta_m = 0;
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} else {
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/* vector */
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delta_m = delta_d;
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}
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}
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}
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f0 = tcg_temp_new_i32();
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fd = tcg_temp_new_i32();
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neon_load_reg32(f0, vm);
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for (;;) {
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fn(fd, f0);
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neon_store_reg32(fd, vd);
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if (veclen == 0) {
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break;
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}
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if (delta_m == 0) {
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/* single source one-many */
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while (veclen--) {
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vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
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neon_store_reg32(fd, vd);
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}
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break;
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}
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/* Set up the operands for the next iteration */
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veclen--;
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vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
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vm = ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask);
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neon_load_reg32(f0, vm);
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}
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tcg_temp_free_i32(f0);
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tcg_temp_free_i32(fd);
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return true;
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}
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static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
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{
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uint32_t delta_m = 0;
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uint32_t delta_d = 0;
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uint32_t bank_mask = 0;
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int veclen = s->vec_len;
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TCGv_i64 f0, fd;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) {
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return false;
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}
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if (!dc_isar_feature(aa32_fpshvec, s) &&
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(veclen != 0 || s->vec_stride != 0)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (veclen > 0) {
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bank_mask = 0xc;
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/* Figure out what type of vector operation this is. */
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if ((vd & bank_mask) == 0) {
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/* scalar */
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veclen = 0;
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} else {
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delta_d = (s->vec_stride >> 1) + 1;
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if ((vm & bank_mask) == 0) {
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/* mixed scalar/vector */
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delta_m = 0;
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} else {
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/* vector */
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delta_m = delta_d;
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}
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}
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}
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f0 = tcg_temp_new_i64();
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fd = tcg_temp_new_i64();
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neon_load_reg64(f0, vm);
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for (;;) {
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fn(fd, f0);
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neon_store_reg64(fd, vd);
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if (veclen == 0) {
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break;
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}
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if (delta_m == 0) {
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/* single source one-many */
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while (veclen--) {
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vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
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neon_store_reg64(fd, vd);
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}
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break;
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}
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/* Set up the operands for the next iteration */
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veclen--;
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vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
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vm = ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask);
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neon_load_reg64(f0, vm);
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}
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tcg_temp_free_i64(f0);
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tcg_temp_free_i64(fd);
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return true;
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}
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static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
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{
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/* Note that order of inputs to the add matters for NaNs */
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@ -1731,3 +1888,13 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
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tcg_temp_free_i64(fd);
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return true;
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}
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static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
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{
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return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
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}
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static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
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{
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return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
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}
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@ -3096,6 +3096,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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case 0 ... 14:
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/* Already handled by decodetree */
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return 1;
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case 15:
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switch (rn) {
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case 1:
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/* Already handled by decodetree */
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return 1;
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default:
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break;
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}
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default:
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break;
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}
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@ -3104,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x00: /* vmov */
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case 0x01: /* vabs */
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case 0x02: /* vneg */
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case 0x03: /* vsqrt */
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break;
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@ -3284,9 +3291,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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case 0: /* cpy */
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/* no-op */
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break;
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case 1: /* abs */
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gen_vfp_abs(dp);
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break;
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case 2: /* neg */
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gen_vfp_neg(dp);
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break;
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@ -156,3 +156,8 @@ VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \
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vd=%vd_sp
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VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \
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vd=%vd_dp
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VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
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vd=%vd_sp vm=%vm_sp
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VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
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vd=%vd_dp vm=%vm_dp
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