hw/arm/armsse: Add unimplemented-device stub for CPU local control registers
The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
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@ -33,6 +33,7 @@ struct ARMSSEInfo {
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bool has_mhus;
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bool has_ppus;
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bool has_cachectrl;
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bool has_cpusecctrl;
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};
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static const ARMSSEInfo armsse_variants[] = {
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@ -45,6 +46,7 @@ static const ARMSSEInfo armsse_variants[] = {
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.has_mhus = false,
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.has_ppus = false,
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.has_cachectrl = false,
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.has_cpusecctrl = false,
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},
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};
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@ -302,6 +304,16 @@ static void armsse_init(Object *obj)
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g_free(name);
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}
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}
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if (info->has_cpusecctrl) {
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for (i = 0; i < info->num_cpus; i++) {
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char *name = g_strdup_printf("cpusecctrl%d", i);
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sysbus_init_child_obj(obj, name, &s->cpusecctrl[i],
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sizeof(s->cpusecctrl[i]),
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TYPE_UNIMPLEMENTED_DEVICE);
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g_free(name);
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}
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}
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object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
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sizeof(s->nmi_orgate), TYPE_OR_IRQ,
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&error_abort, NULL);
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@ -833,6 +845,25 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
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}
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}
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if (info->has_cpusecctrl) {
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for (i = 0; i < info->num_cpus; i++) {
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char *name = g_strdup_printf("CPUSECCTRL%d", i);
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MemoryRegion *mr;
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qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
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g_free(name);
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qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
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object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true,
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"realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0);
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memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr);
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}
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}
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/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
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/* Devices behind APB PPC1:
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@ -151,6 +151,7 @@ typedef struct ARMSSE {
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UnimplementedDeviceState mhu[2];
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UnimplementedDeviceState ppu[NUM_PPUS];
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UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
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UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
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/*
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* 'container' holds all devices seen by all CPUs.
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