target/arm: ARMv8.4-TTST extension
This adds for the Small Translation tables extension in AArch64 state. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3936,6 +3936,11 @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
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}
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}
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static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
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}
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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{
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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@ -10842,7 +10842,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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{
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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bool epd, hpd, using16k, using64k;
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bool epd, hpd, using16k, using64k;
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int select, tsz, tbi;
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int select, tsz, tbi, max_tsz;
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if (!regime_has_2_ranges(mmu_idx)) {
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if (!regime_has_2_ranges(mmu_idx)) {
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select = 0;
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select = 0;
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@ -10877,7 +10877,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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hpd = extract64(tcr, 42, 1);
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hpd = extract64(tcr, 42, 1);
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}
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}
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}
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}
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tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
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if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
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max_tsz = 48 - using64k;
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} else {
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max_tsz = 39;
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}
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tsz = MIN(tsz, max_tsz);
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tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
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tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
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/* Present TBI as a composite with TBID. */
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/* Present TBI as a composite with TBID. */
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@ -11096,6 +11103,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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if (!aarch64 || stride == 9) {
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if (!aarch64 || stride == 9) {
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/* AArch32 or 4KB pages */
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/* AArch32 or 4KB pages */
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startlevel = 2 - sl0;
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startlevel = 2 - sl0;
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if (cpu_isar_feature(aa64_st, cpu)) {
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startlevel &= 3;
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}
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} else {
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} else {
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/* 16KB or 64KB pages */
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/* 16KB or 64KB pages */
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startlevel = 3 - sl0;
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startlevel = 3 - sl0;
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