Implement fast tlb insert insns.
Fix data tlb exception for pa 1.1. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAlzHcoAdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/XIQf+PxRshjRYTLUYL1o1 pWS6/a+YIxOR76UVIjI7XfDaMY3g1yOrwrx5i2T5GmZPcX9kYVPE5quGy/LB/WKL rsgzVMLQ4wKBVituK6hhmldEt6uBcSszcDc7H/HF0EaZfpjdqulmIGU+001dwZ93 i1SunfnsdVC9yWxRiux3xf38lno76hwOTVk2ee6+2oXdkITnpTe7iH/CL88gL12C VvvZgD/o1qASodmZCsXLPLSut/b3KcYy4FRJihPzpFDgdUePKJwireXzR7TeqhLB nOgKzf4twXOCVwrg6qYcUyVDqreL1fXsg+mmk5YFMVQSbl1r1FRefD1krK6ljJT1 vay/9Q== =Xb3F -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190429' into staging Implement fast tlb insert insns. Fix data tlb exception for pa 1.1. # gpg: Signature made Mon 29 Apr 2019 22:54:08 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-hppa-20190429: target/hppa: Always return EXCP_DMAR for protection id trap target/hppa: Implement Fast TLB Insert instructions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
c4bfdd5947
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@ -133,6 +133,9 @@ ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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sp=%assemble_sr3x data=0
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sp=%assemble_sr3x data=0
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# pcxl and pcxl2 Fast TLB Insert instructions
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ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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sp=%assemble_sr3x data=0
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sp=%assemble_sr3x data=0
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@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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if (unlikely(!(prot & type))) {
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if (unlikely(!(prot & type))) {
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/* The access isn't allowed -- Inst/Data Memory Protection Fault. */
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/* The access isn't allowed -- Inst/Data Memory Protection Fault. */
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ret = (type & PAGE_EXEC ? EXCP_IMP :
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ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR;
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prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR);
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goto egress;
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goto egress;
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}
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}
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@ -2518,6 +2518,60 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
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#endif
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#endif
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}
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}
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/*
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* Implement the pcxl and pcxl2 Fast TLB Insert instructions.
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* See
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* https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
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* page 13-9 (195/206)
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*/
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static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
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{
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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TCGv_tl addr, atl, stl;
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TCGv_reg reg;
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nullify_over(ctx);
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/*
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* FIXME:
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* if (not (pcxl or pcxl2))
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* return gen_illegal(ctx);
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*
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* Note for future: these are 32-bit systems; no hppa64.
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*/
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atl = tcg_temp_new_tl();
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stl = tcg_temp_new_tl();
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addr = tcg_temp_new_tl();
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tcg_gen_ld32u_i64(stl, cpu_env,
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a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
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: offsetof(CPUHPPAState, cr[CR_IIASQ]));
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tcg_gen_ld32u_i64(atl, cpu_env,
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a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
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: offsetof(CPUHPPAState, cr[CR_IIAOQ]));
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tcg_gen_shli_i64(stl, stl, 32);
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tcg_gen_or_tl(addr, atl, stl);
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tcg_temp_free_tl(atl);
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tcg_temp_free_tl(stl);
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reg = load_gpr(ctx, a->r);
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if (a->addr) {
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gen_helper_itlba(cpu_env, addr, reg);
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} else {
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gen_helper_itlbp(cpu_env, addr, reg);
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}
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tcg_temp_free_tl(addr);
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/* Exit TB for TLB change if mmu is enabled. */
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if (ctx->tb_flags & PSW_C) {
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ctx->base.is_jmp = DISAS_IAQ_N_STALE;
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}
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return nullify_end(ctx);
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#endif
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}
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static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
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static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
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{
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{
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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