target/arm: Convert VFP fused multiply-add insns to decodetree
Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
519ee7ae31
commit
d4893b01d2
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@ -1481,3 +1481,124 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_sp *a)
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{
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return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
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}
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static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
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{
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/*
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* VFNMA : fd = muladd(-fd, fn, fm)
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* VFNMS : fd = muladd(-fd, -fn, fm)
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* VFMA : fd = muladd( fd, fn, fm)
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* VFMS : fd = muladd( fd, -fn, fm)
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*
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* These are fused multiply-add, and must be done as one floating
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* point operation with no rounding between the multiplication and
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* addition steps. NB that doing the negations here as separate
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* steps is correct : an input NaN should come out with its sign
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* bit flipped if it is a negated-input.
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*/
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TCGv_ptr fpst;
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TCGv_i32 vn, vm, vd;
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/*
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* Present in VFPv4 only.
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* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
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* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
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(s->vec_len != 0 || s->vec_stride != 0)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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vn = tcg_temp_new_i32();
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vm = tcg_temp_new_i32();
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vd = tcg_temp_new_i32();
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neon_load_reg32(vn, a->vn);
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neon_load_reg32(vm, a->vm);
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if (a->o2) {
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/* VFNMS, VFMS */
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gen_helper_vfp_negs(vn, vn);
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}
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neon_load_reg32(vd, a->vd);
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if (a->o1 & 1) {
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/* VFNMA, VFNMS */
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gen_helper_vfp_negs(vd, vd);
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}
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fpst = get_fpstatus_ptr(0);
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gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
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neon_store_reg32(vd, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(vn);
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tcg_temp_free_i32(vm);
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tcg_temp_free_i32(vd);
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return true;
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}
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static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a)
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{
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/*
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* VFNMA : fd = muladd(-fd, fn, fm)
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* VFNMS : fd = muladd(-fd, -fn, fm)
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* VFMA : fd = muladd( fd, fn, fm)
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* VFMS : fd = muladd( fd, -fn, fm)
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*
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* These are fused multiply-add, and must be done as one floating
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* point operation with no rounding between the multiplication and
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* addition steps. NB that doing the negations here as separate
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* steps is correct : an input NaN should come out with its sign
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* bit flipped if it is a negated-input.
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*/
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TCGv_ptr fpst;
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TCGv_i64 vn, vm, vd;
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/*
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* Present in VFPv4 only.
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* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
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* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
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(s->vec_len != 0 || s->vec_stride != 0)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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vn = tcg_temp_new_i64();
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vm = tcg_temp_new_i64();
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vd = tcg_temp_new_i64();
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neon_load_reg64(vn, a->vn);
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neon_load_reg64(vm, a->vm);
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if (a->o2) {
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/* VFNMS, VFMS */
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gen_helper_vfp_negd(vn, vn);
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}
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neon_load_reg64(vd, a->vd);
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if (a->o1 & 1) {
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/* VFNMA, VFNMS */
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gen_helper_vfp_negd(vd, vd);
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}
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fpst = get_fpstatus_ptr(0);
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gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
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neon_store_reg64(vd, a->vd);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(vn);
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tcg_temp_free_i64(vm);
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tcg_temp_free_i64(vd);
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return true;
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}
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@ -3093,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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rn = VFP_SREG_N(insn);
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switch (op) {
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case 0 ... 8:
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case 0 ... 13:
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/* Already handled by decodetree */
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return 1;
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default:
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@ -3279,57 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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for (;;) {
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/* Perform the calculation. */
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switch (op) {
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case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
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case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
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case 12: /* VFMA : fd = muladd( fd, fn, fm) */
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case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
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/* These are fused multiply-add, and must be done as one
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* floating point operation with no rounding between the
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* multiplication and addition steps.
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* NB that doing the negations here as separate steps is
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* correct : an input NaN should come out with its sign bit
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* flipped if it is a negated-input.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
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return 1;
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}
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if (dp) {
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TCGv_ptr fpst;
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TCGv_i64 frd;
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if (op & 1) {
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/* VFNMS, VFMS */
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gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
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}
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frd = tcg_temp_new_i64();
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tcg_gen_ld_f64(frd, cpu_env, vfp_reg_offset(dp, rd));
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if (op & 2) {
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/* VFNMA, VFNMS */
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gen_helper_vfp_negd(frd, frd);
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}
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fpst = get_fpstatus_ptr(0);
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gen_helper_vfp_muladdd(cpu_F0d, cpu_F0d,
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cpu_F1d, frd, fpst);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(frd);
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} else {
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TCGv_ptr fpst;
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TCGv_i32 frd;
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if (op & 1) {
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/* VFNMS, VFMS */
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gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
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}
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frd = tcg_temp_new_i32();
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tcg_gen_ld_f32(frd, cpu_env, vfp_reg_offset(dp, rd));
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if (op & 2) {
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gen_helper_vfp_negs(frd, frd);
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}
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fpst = get_fpstatus_ptr(0);
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gen_helper_vfp_muladds(cpu_F0s, cpu_F0s,
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cpu_F1s, frd, fpst);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(frd);
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}
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break;
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case 14: /* fconst */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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@ -142,3 +142,12 @@ VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp
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VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
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VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
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VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2
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VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
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