armv7m: FAULTMASK should be 0 on reset
For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK. QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the I bit) we have to clear these to undo the A profile default of 1. Update the comment accordingly and move it so that it's closer to the code it's referring to. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-10-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message, moved comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC;
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env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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* clear at reset. Initial SP and PC are loaded from ROM.
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*/
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if (arm_feature(env, ARM_FEATURE_M)) {
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uint32_t initial_msp; /* Loaded from 0x0 */
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uint32_t initial_pc; /* Loaded from 0x4 */
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uint8_t *rom;
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env->daif &= ~PSTATE_I;
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/* For M profile we store FAULTMASK and PRIMASK in the
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* PSTATE F and I bits; these are both clear at reset.
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*/
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env->daif &= ~(PSTATE_I | PSTATE_F);
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/* The reset value of this bit is IMPDEF, but ARM recommends
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* that it resets to 1, so QEMU always does that rather than making
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@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
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*/
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env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
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/* Load the initial SP and PC from the vector table at address 0 */
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rom = rom_ptr(0);
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if (rom) {
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/* Address zero is covered by ROM which hasn't yet been
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