haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

stellaris: Don't hw_error() on bad register accesses

Browse source 
Current recommended style is to log a guest error on bad register
accesses, not kill the whole system with hw_error().  Change the
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
g_assert_not_reached() as appropriate.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-04-20 17:32:29 +01:00
parent 65ed2ed90d
commit df3692e04b
1 changed files with 37 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

60
hw/arm/stellaris.c
View file

@ -108,7 +108,10 @@ static void gptm_reload(gptm_state *s, int n, int reset)
} else if (s->mode[n] == 0xa) { } else if (s->mode[n] == 0xa) {
/* PWM mode. Not implemented. */ /* PWM mode. Not implemented. */
} else { } else {
hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); qemu_log_mask(LOG_UNIMP,
"GPTM: 16-bit timer mode unimplemented: 0x%x\n",
s->mode[n]);
return;
} }
s->tick[n] = tick; s->tick[n] = tick;
timer_mod(s->timer[n], tick); timer_mod(s->timer[n], tick);
@ -149,7 +152,9 @@ static void gptm_tick(void *opaque)
} else if (s->mode[n] == 0xa) { } else if (s->mode[n] == 0xa) {
/* PWM mode. Not implemented. */ /* PWM mode. Not implemented. */
} else { } else {
hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); qemu_log_mask(LOG_UNIMP,
"GPTM: 16-bit timer mode unimplemented: 0x%x\n",
s->mode[n]);
} }
gptm_update_irq(s); gptm_update_irq(s);
} }
@ -286,7 +291,8 @@ static void gptm_write(void *opaque, hwaddr offset,
s->match_prescale[0] = value; s->match_prescale[0] = value;
break; break;
default: default:
hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"GPTM: read at bad offset 0x%x\n", (int)offset);
} }
gptm_update_irq(s); gptm_update_irq(s);
} }
@ -425,7 +431,10 @@ static int ssys_board_class(const ssys_state *s)
} }
/* for unknown classes, fall through */ /* for unknown classes, fall through */
default: default:
hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); /* This can only happen if the hardwired constant did0 value
* in this board's stellaris_board_info struct is wrong.
*/
g_assert_not_reached();
} }
} }
@ -479,8 +488,7 @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
case DID0_CLASS_SANDSTORM: case DID0_CLASS_SANDSTORM:
return pllcfg_sandstorm[xtal]; return pllcfg_sandstorm[xtal];
default: default:
hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); g_assert_not_reached();
return 0;
} }
} }
case 0x070: /* RCC2 */ case 0x070: /* RCC2 */
@ -512,7 +520,8 @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
case 0x1e4: /* USER1 */ case 0x1e4: /* USER1 */
return s->user1; return s->user1;
default: default:
hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"SSYS: read at bad offset 0x%x\n", (int)offset);
return 0; return 0;
} }
} }
@ -614,7 +623,8 @@ static void ssys_write(void *opaque, hwaddr offset,
s->ldoarst = value; s->ldoarst = value;
break; break;
default: default:
hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"SSYS: write at bad offset 0x%x\n", (int)offset);
} }
ssys_update(s); ssys_update(s);
} }
@ -748,7 +758,8 @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
case 0x20: /* MCR */ case 0x20: /* MCR */
return s->mcr; return s->mcr;
default: default:
hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
return 0; return 0;
} }
} }
@ -823,17 +834,18 @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
s->mris &= ~value; s->mris &= ~value;
break; break;
case 0x20: /* MCR */ case 0x20: /* MCR */
if (value & 1) if (value & 1) {
hw_error( qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
"stellaris_i2c_write: Loopback not implemented\n"); }
if (value & 0x20) if (value & 0x20) {
hw_error( qemu_log_mask(LOG_UNIMP,
"stellaris_i2c_write: Slave mode not implemented\n"); "stellaris_i2c: Slave mode not implemented");
}
s->mcr = value & 0x31; s->mcr = value & 0x31;
break; break;
default: default:
hw_error("stellaris_i2c_write: Bad offset 0x%x\n", qemu_log_mask(LOG_GUEST_ERROR,
(int)offset); "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
} }
stellaris_i2c_update(s); stellaris_i2c_update(s);
} }
@ -1057,8 +1069,8 @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
case 0x30: /* SAC */ case 0x30: /* SAC */
return s->sac; return s->sac;
default: default:
hw_error("strllaris_adc_read: Bad offset 0x%x\n", qemu_log_mask(LOG_GUEST_ERROR,
(int)offset); "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
return 0; return 0;
} }
} }
@ -1078,8 +1090,9 @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
return; return;
case 0x04: /* SSCTL */ case 0x04: /* SSCTL */
if (value != 6) { if (value != 6) {
hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", qemu_log_mask(LOG_UNIMP,
value); "ADC: Unimplemented sequence %" PRIx64 "\n",
value);
} }
s->ssctl[n] = value; s->ssctl[n] = value;
return; return;
@ -1110,13 +1123,14 @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
s->sspri = value; s->sspri = value;
break; break;
case 0x28: /* PSSI */ case 0x28: /* PSSI */
hw_error("Not implemented: ADC sample initiate\n"); qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
break; break;
case 0x30: /* SAC */ case 0x30: /* SAC */
s->sac = value; s->sac = value;
break; break;
default: default:
hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"stellaris_adc: write at bad offset 0x%x\n", (int)offset);
} }
stellaris_adc_update(s); stellaris_adc_update(s);
} }