ARM: exynos4210: UART support
Add basic support of exynos4210 UART Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
0caa711335
commit
e5a4914efc
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@ -345,7 +345,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
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obj-arm-y += versatile_pci.o
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obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-arm-y += exynos4_boards.o
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obj-arm-y += exynos4_boards.o exynos4210_uart.o
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obj-arm-y += arm_l2x0.o
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obj-arm-y += arm_mptimer.o
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obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
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@ -29,6 +29,18 @@
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#define EXYNOS4210_CHIPID_ADDR 0x10000000
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/* UART's definitions */
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#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
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#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
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#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
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#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
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#define EXYNOS4210_UART0_FIFO_SIZE 256
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#define EXYNOS4210_UART1_FIFO_SIZE 64
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#define EXYNOS4210_UART2_FIFO_SIZE 16
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#define EXYNOS4210_UART3_FIFO_SIZE 16
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/* Interrupt Group of External Interrupt Combiner for UART */
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#define EXYNOS4210_UART_INT_GRP 26
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/* External GIC */
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#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
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#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
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@ -187,5 +199,22 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
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&s->dram0_mem);
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/*** UARTs ***/
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exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
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EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
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exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
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EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
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exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
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EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
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exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
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EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
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return s;
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}
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@ -119,4 +119,13 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
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void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
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int ext);
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/*
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* exynos4210 UART
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*/
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DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
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int fifo_size,
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int channel,
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CharDriverState *chr,
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qemu_irq irq);
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#endif /* EXYNOS4210_H_ */
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676
hw/exynos4210_uart.c
Normal file
676
hw/exynos4210_uart.c
Normal file
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@ -0,0 +1,676 @@
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/*
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* Exynos4210 UART Emulation
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*
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* Copyright (C) 2011 Samsung Electronics Co Ltd.
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* Maksim Kozlov, <m.kozlov@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "sysbus.h"
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#include "sysemu.h"
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#include "qemu-char.h"
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#include "exynos4210.h"
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#undef DEBUG_UART
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#undef DEBUG_UART_EXTEND
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#undef DEBUG_IRQ
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#undef DEBUG_Rx_DATA
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#undef DEBUG_Tx_DATA
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#define DEBUG_UART 0
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#define DEBUG_UART_EXTEND 0
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#define DEBUG_IRQ 0
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#define DEBUG_Rx_DATA 0
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#define DEBUG_Tx_DATA 0
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#if DEBUG_UART
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#define PRINT_DEBUG(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
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} while (0)
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#if DEBUG_UART_EXTEND
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
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} while (0)
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#else
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do {} while (0)
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#endif /* EXTEND */
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#else
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#define PRINT_DEBUG(fmt, args...) \
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do {} while (0)
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#define PRINT_DEBUG_EXTEND(fmt, args...) \
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do {} while (0)
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#endif
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#define PRINT_ERROR(fmt, args...) \
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do { \
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fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
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} while (0)
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/*
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* Offsets for UART registers relative to SFR base address
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* for UARTn
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*
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*/
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#define ULCON 0x0000 /* Line Control */
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#define UCON 0x0004 /* Control */
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#define UFCON 0x0008 /* FIFO Control */
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#define UMCON 0x000C /* Modem Control */
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#define UTRSTAT 0x0010 /* Tx/Rx Status */
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#define UERSTAT 0x0014 /* UART Error Status */
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#define UFSTAT 0x0018 /* FIFO Status */
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#define UMSTAT 0x001C /* Modem Status */
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#define UTXH 0x0020 /* Transmit Buffer */
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#define URXH 0x0024 /* Receive Buffer */
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#define UBRDIV 0x0028 /* Baud Rate Divisor */
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#define UFRACVAL 0x002C /* Divisor Fractional Value */
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#define UINTP 0x0030 /* Interrupt Pending */
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#define UINTSP 0x0034 /* Interrupt Source Pending */
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#define UINTM 0x0038 /* Interrupt Mask */
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/*
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* for indexing register in the uint32_t array
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*
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* 'reg' - register offset (see offsets definitions above)
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*
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*/
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#define I_(reg) (reg / sizeof(uint32_t))
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typedef struct Exynos4210UartReg {
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const char *name; /* the only reason is the debug output */
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target_phys_addr_t offset;
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uint32_t reset_value;
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} Exynos4210UartReg;
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static Exynos4210UartReg exynos4210_uart_regs[] = {
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{"ULCON", ULCON, 0x00000000},
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{"UCON", UCON, 0x00003000},
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{"UFCON", UFCON, 0x00000000},
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{"UMCON", UMCON, 0x00000000},
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{"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
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{"UERSTAT", UERSTAT, 0x00000000}, /* RO */
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{"UFSTAT", UFSTAT, 0x00000000}, /* RO */
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{"UMSTAT", UMSTAT, 0x00000000}, /* RO */
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{"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
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{"URXH", URXH, 0x00000000}, /* RO */
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{"UBRDIV", UBRDIV, 0x00000000},
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{"UFRACVAL", UFRACVAL, 0x00000000},
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{"UINTP", UINTP, 0x00000000},
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{"UINTSP", UINTSP, 0x00000000},
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{"UINTM", UINTM, 0x00000000},
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};
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#define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
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/* UART FIFO Control */
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#define UFCON_FIFO_ENABLE 0x1
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#define UFCON_Rx_FIFO_RESET 0x2
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#define UFCON_Tx_FIFO_RESET 0x4
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
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/* Uart FIFO Status */
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#define UFSTAT_Rx_FIFO_COUNT 0xff
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#define UFSTAT_Rx_FIFO_FULL 0x100
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#define UFSTAT_Rx_FIFO_ERROR 0x200
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#define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
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#define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
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#define UFSTAT_Tx_FIFO_FULL_SHIFT 24
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#define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
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/* UART Interrupt Source Pending */
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#define UINTSP_RXD 0x1 /* Receive interrupt */
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#define UINTSP_ERROR 0x2 /* Error interrupt */
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#define UINTSP_TXD 0x4 /* Transmit interrupt */
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#define UINTSP_MODEM 0x8 /* Modem interrupt */
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/* UART Line Control */
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#define ULCON_IR_MODE_SHIFT 6
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#define ULCON_PARITY_SHIFT 3
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#define ULCON_STOP_BIT_SHIFT 1
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/* UART Tx/Rx Status */
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#define UTRSTAT_TRANSMITTER_EMPTY 0x4
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#define UTRSTAT_Tx_BUFFER_EMPTY 0x2
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#define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
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/* UART Error Status */
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#define UERSTAT_OVERRUN 0x1
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#define UERSTAT_PARITY 0x2
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#define UERSTAT_FRAME 0x4
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#define UERSTAT_BREAK 0x8
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typedef struct {
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uint8_t *data;
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uint32_t sp, rp; /* store and retrieve pointers */
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uint32_t size;
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} Exynos4210UartFIFO;
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
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Exynos4210UartFIFO rx;
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Exynos4210UartFIFO tx;
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t channel;
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} Exynos4210UartState;
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#if DEBUG_UART
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/* Used only for debugging inside PRINT_DEBUG_... macros */
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static const char *exynos4210_uart_regname(target_phys_addr_t offset)
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{
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int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
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int i;
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for (i = 0; i < regs_number; i++) {
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if (offset == exynos4210_uart_regs[i].offset) {
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return exynos4210_uart_regs[i].name;
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}
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}
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return NULL;
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}
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#endif
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static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
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{
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q->data[q->sp] = ch;
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q->sp = (q->sp + 1) % q->size;
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}
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static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
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{
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uint8_t ret = q->data[q->rp];
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q->rp = (q->rp + 1) % q->size;
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return ret;
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}
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static int fifo_elements_number(Exynos4210UartFIFO *q)
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{
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if (q->sp < q->rp) {
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return q->size - q->rp + q->sp;
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}
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return q->sp - q->rp;
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}
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static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
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{
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return q->size - fifo_elements_number(q);
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}
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static void fifo_reset(Exynos4210UartFIFO *q)
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{
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if (q->data != NULL) {
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g_free(q->data);
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q->data = NULL;
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}
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q->data = (uint8_t *)g_malloc0(q->size);
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q->sp = 0;
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q->rp = 0;
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}
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static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
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{
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uint32_t level = 0;
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uint32_t reg;
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reg = (s->reg[I_(UFCON)] && UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
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UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
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switch (s->channel) {
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case 0:
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level = reg * 32;
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break;
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case 1:
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case 4:
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level = reg * 8;
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break;
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case 2:
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case 3:
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level = reg * 2;
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break;
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default:
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level = 0;
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PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
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}
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return level;
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}
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static void exynos4210_uart_update_irq(Exynos4210UartState *s)
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{
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/*
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* The Tx interrupt is always requested if the number of data in the
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* transmit FIFO is smaller than the trigger level.
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*/
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if (s->reg[I_(UFCON)] && UFCON_FIFO_ENABLE) {
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uint32_t count = (s->reg[I_(UFSTAT)] && UFSTAT_Tx_FIFO_COUNT) >>
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UFSTAT_Tx_FIFO_COUNT_SHIFT;
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if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
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s->reg[I_(UINTSP)] |= UINTSP_TXD;
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}
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}
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s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
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if (s->reg[I_(UINTP)]) {
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qemu_irq_raise(s->irq);
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#if DEBUG_IRQ
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fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
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s->channel, s->reg[I_(UINTP)]);
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#endif
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
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{
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp;
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uint64_t uclk_rate;
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if (s->reg[I_(UBRDIV)] == 0) {
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return;
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}
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frame_size = 1; /* start bit */
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if (s->reg[I_(ULCON)] & 0x20) {
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frame_size++; /* parity bit */
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if (s->reg[I_(ULCON)] & 0x28) {
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parity = 'E';
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} else {
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parity = 'O';
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}
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} else {
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parity = 'N';
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}
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if (s->reg[I_(ULCON)] & 0x4) {
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stop_bits = 2;
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} else {
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stop_bits = 1;
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}
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data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
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frame_size += data_bits + stop_bits;
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uclk_rate = 24000000;
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speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
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(s->reg[I_(UFRACVAL)] & 0x7) + 16);
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
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s->channel, speed, parity, data_bits, stop_bits);
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}
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static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
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uint64_t val, unsigned size)
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{
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Exynos4210UartState *s = (Exynos4210UartState *)opaque;
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uint8_t ch;
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PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
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offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
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switch (offset) {
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case ULCON:
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case UBRDIV:
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case UFRACVAL:
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s->reg[I_(offset)] = val;
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exynos4210_uart_update_parameters(s);
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break;
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case UFCON:
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s->reg[I_(UFCON)] = val;
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if (val & UFCON_Rx_FIFO_RESET) {
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fifo_reset(&s->rx);
|
||||
s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
|
||||
PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
|
||||
}
|
||||
if (val & UFCON_Tx_FIFO_RESET) {
|
||||
fifo_reset(&s->tx);
|
||||
s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
|
||||
PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
|
||||
}
|
||||
break;
|
||||
|
||||
case UTXH:
|
||||
if (s->chr) {
|
||||
s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
|
||||
UTRSTAT_Tx_BUFFER_EMPTY);
|
||||
ch = (uint8_t)val;
|
||||
qemu_chr_fe_write(s->chr, &ch, 1);
|
||||
#if DEBUG_Tx_DATA
|
||||
fprintf(stderr, "%c", ch);
|
||||
#endif
|
||||
s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
|
||||
UTRSTAT_Tx_BUFFER_EMPTY;
|
||||
s->reg[I_(UINTSP)] |= UINTSP_TXD;
|
||||
exynos4210_uart_update_irq(s);
|
||||
}
|
||||
break;
|
||||
|
||||
case UINTP:
|
||||
s->reg[I_(UINTP)] &= ~val;
|
||||
s->reg[I_(UINTSP)] &= ~val;
|
||||
PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
|
||||
s->channel, offset, s->reg[I_(UINTP)]);
|
||||
exynos4210_uart_update_irq(s);
|
||||
break;
|
||||
case UTRSTAT:
|
||||
case UERSTAT:
|
||||
case UFSTAT:
|
||||
case UMSTAT:
|
||||
case URXH:
|
||||
PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
|
||||
s->channel, exynos4210_uart_regname(offset), offset);
|
||||
break;
|
||||
case UINTSP:
|
||||
s->reg[I_(UINTSP)] &= ~val;
|
||||
break;
|
||||
case UINTM:
|
||||
s->reg[I_(UINTM)] = val;
|
||||
exynos4210_uart_update_irq(s);
|
||||
break;
|
||||
case UCON:
|
||||
case UMCON:
|
||||
default:
|
||||
s->reg[I_(offset)] = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
static uint64_t exynos4210_uart_read(void *opaque, target_phys_addr_t offset,
|
||||
unsigned size)
|
||||
{
|
||||
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
||||
uint32_t res;
|
||||
|
||||
switch (offset) {
|
||||
case UERSTAT: /* Read Only */
|
||||
res = s->reg[I_(UERSTAT)];
|
||||
s->reg[I_(UERSTAT)] = 0;
|
||||
return res;
|
||||
case UFSTAT: /* Read Only */
|
||||
s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
|
||||
if (fifo_empty_elements_number(&s->rx) == 0) {
|
||||
s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
|
||||
s->reg[I_(UFSTAT)] &= ~0xff;
|
||||
}
|
||||
return s->reg[I_(UFSTAT)];
|
||||
case URXH:
|
||||
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
||||
if (fifo_elements_number(&s->rx)) {
|
||||
res = fifo_retrieve(&s->rx);
|
||||
#if DEBUG_Rx_DATA
|
||||
fprintf(stderr, "%c", res);
|
||||
#endif
|
||||
if (!fifo_elements_number(&s->rx)) {
|
||||
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
} else {
|
||||
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
}
|
||||
} else {
|
||||
s->reg[I_(UINTSP)] |= UINTSP_ERROR;
|
||||
exynos4210_uart_update_irq(s);
|
||||
res = 0;
|
||||
}
|
||||
} else {
|
||||
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
res = s->reg[I_(URXH)];
|
||||
}
|
||||
return res;
|
||||
case UTXH:
|
||||
PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
|
||||
s->channel, exynos4210_uart_regname(offset), offset);
|
||||
break;
|
||||
default:
|
||||
return s->reg[I_(offset)];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps exynos4210_uart_ops = {
|
||||
.read = exynos4210_uart_read,
|
||||
.write = exynos4210_uart_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.max_access_size = 4,
|
||||
.unaligned = false
|
||||
},
|
||||
};
|
||||
|
||||
static int exynos4210_uart_can_receive(void *opaque)
|
||||
{
|
||||
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
||||
|
||||
return fifo_empty_elements_number(&s->rx);
|
||||
}
|
||||
|
||||
|
||||
static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
|
||||
{
|
||||
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
||||
int i;
|
||||
|
||||
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
||||
if (fifo_empty_elements_number(&s->rx) < size) {
|
||||
for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
|
||||
fifo_store(&s->rx, buf[i]);
|
||||
}
|
||||
s->reg[I_(UINTSP)] |= UINTSP_ERROR;
|
||||
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
} else {
|
||||
for (i = 0; i < size; i++) {
|
||||
fifo_store(&s->rx, buf[i]);
|
||||
}
|
||||
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
}
|
||||
/* XXX: Around here we maybe should check Rx trigger level */
|
||||
s->reg[I_(UINTSP)] |= UINTSP_RXD;
|
||||
} else {
|
||||
s->reg[I_(URXH)] = buf[0];
|
||||
s->reg[I_(UINTSP)] |= UINTSP_RXD;
|
||||
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
||||
}
|
||||
|
||||
exynos4210_uart_update_irq(s);
|
||||
}
|
||||
|
||||
|
||||
static void exynos4210_uart_event(void *opaque, int event)
|
||||
{
|
||||
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
||||
|
||||
if (event == CHR_EVENT_BREAK) {
|
||||
/* When the RxDn is held in logic 0, then a null byte is pushed into the
|
||||
* fifo */
|
||||
fifo_store(&s->rx, '\0');
|
||||
s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
|
||||
exynos4210_uart_update_irq(s);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void exynos4210_uart_reset(DeviceState *dev)
|
||||
{
|
||||
Exynos4210UartState *s =
|
||||
container_of(dev, Exynos4210UartState, busdev.qdev);
|
||||
int regs_number = sizeof(exynos4210_uart_regs)/sizeof(Exynos4210UartReg);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < regs_number; i++) {
|
||||
s->reg[I_(exynos4210_uart_regs[i].offset)] =
|
||||
exynos4210_uart_regs[i].reset_value;
|
||||
}
|
||||
|
||||
fifo_reset(&s->rx);
|
||||
fifo_reset(&s->tx);
|
||||
|
||||
PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_exynos4210_uart_fifo = {
|
||||
.name = "exynos4210.uart.fifo",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(sp, Exynos4210UartFIFO),
|
||||
VMSTATE_UINT32(rp, Exynos4210UartFIFO),
|
||||
VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_exynos4210_uart = {
|
||||
.name = "exynos4210.uart",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
|
||||
vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
|
||||
VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
|
||||
EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
|
||||
int fifo_size,
|
||||
int channel,
|
||||
CharDriverState *chr,
|
||||
qemu_irq irq)
|
||||
{
|
||||
DeviceState *dev;
|
||||
SysBusDevice *bus;
|
||||
|
||||
const char chr_name[] = "serial";
|
||||
char label[ARRAY_SIZE(chr_name) + 1];
|
||||
|
||||
dev = qdev_create(NULL, "exynos4210.uart");
|
||||
|
||||
if (!chr) {
|
||||
if (channel >= MAX_SERIAL_PORTS) {
|
||||
hw_error("Only %d serial ports are supported by QEMU.\n",
|
||||
MAX_SERIAL_PORTS);
|
||||
}
|
||||
chr = serial_hds[channel];
|
||||
if (!chr) {
|
||||
snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
|
||||
chr = qemu_chr_new(label, "null", NULL);
|
||||
if (!(chr)) {
|
||||
hw_error("Can't assign serial port to UART%d.\n", channel);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
qdev_prop_set_chr(dev, "chardev", chr);
|
||||
qdev_prop_set_uint32(dev, "channel", channel);
|
||||
qdev_prop_set_uint32(dev, "rx-size", fifo_size);
|
||||
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
|
||||
|
||||
bus = sysbus_from_qdev(dev);
|
||||
qdev_init_nofail(dev);
|
||||
if (addr != (target_phys_addr_t)-1) {
|
||||
sysbus_mmio_map(bus, 0, addr);
|
||||
}
|
||||
sysbus_connect_irq(bus, 0, irq);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
static int exynos4210_uart_init(SysBusDevice *dev)
|
||||
{
|
||||
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
|
||||
|
||||
/* memory mapping */
|
||||
memory_region_init_io(&s->iomem, &exynos4210_uart_ops, s, "exynos4210.uart",
|
||||
EXYNOS4210_UART_REGS_MEM_SIZE);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
|
||||
qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
|
||||
exynos4210_uart_receive, exynos4210_uart_event, s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static Property exynos4210_uart_properties[] = {
|
||||
DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
|
||||
DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
|
||||
DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
|
||||
DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
k->init = exynos4210_uart_init;
|
||||
dc->reset = exynos4210_uart_reset;
|
||||
dc->props = exynos4210_uart_properties;
|
||||
dc->vmsd = &vmstate_exynos4210_uart;
|
||||
}
|
||||
|
||||
static TypeInfo exynos4210_uart_info = {
|
||||
.name = "exynos4210.uart",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(Exynos4210UartState),
|
||||
.class_init = exynos4210_uart_class_init,
|
||||
};
|
||||
|
||||
static void exynos4210_uart_register(void)
|
||||
{
|
||||
type_register_static(&exynos4210_uart_info);
|
||||
}
|
||||
|
||||
type_init(exynos4210_uart_register)
|
Loading…
Reference in a new issue