hw/intc/gicv3: Add defines for ICH system register fields
Add defines to gicv3_internal.h for fields in the ICH_* system registers which form the GIC virtualization control interface. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-7-git-send-email-peter.maydell@linaro.org
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#define ICC_CTLR_EL3_A3V (1U << 15)
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#define ICC_CTLR_EL3_NDS (1U << 17)
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#define ICH_VMCR_EL2_VENG0_SHIFT 0
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#define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
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#define ICH_VMCR_EL2_VENG1_SHIFT 1
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#define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT)
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#define ICH_VMCR_EL2_VACKCTL (1U << 2)
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#define ICH_VMCR_EL2_VFIQEN (1U << 3)
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#define ICH_VMCR_EL2_VCBPR_SHIFT 4
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#define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT)
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#define ICH_VMCR_EL2_VEOIM_SHIFT 9
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#define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT)
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#define ICH_VMCR_EL2_VBPR1_SHIFT 18
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#define ICH_VMCR_EL2_VBPR1_LENGTH 3
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#define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT)
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#define ICH_VMCR_EL2_VBPR0_SHIFT 21
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#define ICH_VMCR_EL2_VBPR0_LENGTH 3
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#define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
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#define ICH_VMCR_EL2_VPMR_SHIFT 24
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#define ICH_VMCR_EL2_VPMR_LENGTH 8
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#define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT)
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#define ICH_HCR_EL2_EN (1U << 0)
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#define ICH_HCR_EL2_UIE (1U << 1)
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#define ICH_HCR_EL2_LRENPIE (1U << 2)
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#define ICH_HCR_EL2_NPIE (1U << 3)
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#define ICH_HCR_EL2_VGRP0EIE (1U << 4)
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#define ICH_HCR_EL2_VGRP0DIE (1U << 5)
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#define ICH_HCR_EL2_VGRP1EIE (1U << 6)
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#define ICH_HCR_EL2_VGRP1DIE (1U << 7)
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#define ICH_HCR_EL2_TC (1U << 10)
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#define ICH_HCR_EL2_TALL0 (1U << 11)
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#define ICH_HCR_EL2_TALL1 (1U << 12)
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#define ICH_HCR_EL2_TSEI (1U << 13)
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#define ICH_HCR_EL2_TDIR (1U << 14)
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#define ICH_HCR_EL2_EOICOUNT_SHIFT 27
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#define ICH_HCR_EL2_EOICOUNT_LENGTH 5
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#define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT)
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#define ICH_LR_EL2_VINTID_SHIFT 0
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#define ICH_LR_EL2_VINTID_LENGTH 32
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#define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT)
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#define ICH_LR_EL2_PINTID_SHIFT 32
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#define ICH_LR_EL2_PINTID_LENGTH 10
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#define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT)
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/* Note that EOI shares with the top bit of the pINTID field */
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#define ICH_LR_EL2_EOI (1ULL << 41)
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#define ICH_LR_EL2_PRIORITY_SHIFT 48
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#define ICH_LR_EL2_PRIORITY_LENGTH 8
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#define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
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#define ICH_LR_EL2_GROUP (1ULL << 60)
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#define ICH_LR_EL2_HW (1ULL << 61)
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#define ICH_LR_EL2_STATE_SHIFT 62
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#define ICH_LR_EL2_STATE_LENGTH 2
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#define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT)
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/* values for the state field: */
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#define ICH_LR_EL2_STATE_INVALID 0
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#define ICH_LR_EL2_STATE_PENDING 1
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#define ICH_LR_EL2_STATE_ACTIVE 2
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#define ICH_LR_EL2_STATE_ACTIVE_PENDING 3
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#define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT)
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#define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT)
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#define ICH_MISR_EL2_EOI (1U << 0)
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#define ICH_MISR_EL2_U (1U << 1)
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#define ICH_MISR_EL2_LRENP (1U << 2)
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#define ICH_MISR_EL2_NP (1U << 3)
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#define ICH_MISR_EL2_VGRP0E (1U << 4)
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#define ICH_MISR_EL2_VGRP0D (1U << 5)
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#define ICH_MISR_EL2_VGRP1E (1U << 6)
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#define ICH_MISR_EL2_VGRP1D (1U << 7)
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#define ICH_VTR_EL2_LISTREGS_SHIFT 0
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#define ICH_VTR_EL2_TDS (1U << 19)
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#define ICH_VTR_EL2_NV4 (1U << 20)
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#define ICH_VTR_EL2_A3V (1U << 21)
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#define ICH_VTR_EL2_SEIS (1U << 22)
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#define ICH_VTR_EL2_IDBITS_SHIFT 23
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#define ICH_VTR_EL2_PREBITS_SHIFT 26
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#define ICH_VTR_EL2_PRIBITS_SHIFT 29
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/* Special interrupt IDs */
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#define INTID_SECURE 1020
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#define INTID_NONSECURE 1021
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