ppc/pnv: Extend XiveRouter with a get_block_id() handler
When doing CAM line compares, fetch the block id from the interrupt controller which can have set the PC_TCTXT_CHIPID field. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191125065820.927-20-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -459,6 +459,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
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return count;
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}
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static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
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{
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return pnv_xive_block_id(PNV_XIVE(xrtr));
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}
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/*
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* The TIMA MMIO space is shared among the chips and to identify the
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* chip from which the access is being done, we extract the chip id
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@ -1890,6 +1895,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
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xrc->write_end = pnv_xive_write_end;
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xrc->get_nvt = pnv_xive_get_nvt;
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xrc->write_nvt = pnv_xive_write_nvt;
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xrc->get_block_id = pnv_xive_get_block_id;
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xnc->notify = pnv_xive_notify;
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xpc->match_nvt = pnv_xive_match_nvt;
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@ -473,6 +473,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
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return count;
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}
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static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
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{
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return SPAPR_XIVE_BLOCK_ID;
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}
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static const VMStateDescription vmstate_spapr_xive_end = {
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.name = TYPE_SPAPR_XIVE "/end",
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.version_id = 1,
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@ -766,6 +771,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
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xrc->write_end = spapr_xive_write_end;
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xrc->get_nvt = spapr_xive_get_nvt;
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xrc->write_nvt = spapr_xive_write_nvt;
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xrc->get_block_id = spapr_xive_get_block_id;
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sicc->activate = spapr_xive_activate;
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sicc->deactivate = spapr_xive_deactivate;
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@ -1371,17 +1371,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
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}
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static int xive_router_get_block_id(XiveRouter *xrtr)
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{
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XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
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return xrc->get_block_id(xrtr);
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}
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/*
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* Encode the HW CAM line in the block group mode format :
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*
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* chip << 19 | 0000000 0 0001 thread (7Bit)
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*/
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static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
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static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
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{
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CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
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uint32_t pir = env->spr_cb[SPR_PIR].default_value;
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uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
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return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
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return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
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}
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/*
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@ -1418,7 +1426,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
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/* PHYS ring */
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if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
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cam == xive_tctx_hw_cam_line(tctx)) {
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cam == xive_tctx_hw_cam_line(xptr, tctx)) {
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return TM_QW3_HV_PHYS;
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}
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@ -1755,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
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uint8_t pq;
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uint64_t ret = -1;
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end_blk = xsrc->block_id;
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/*
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* The block id should be deduced from the load address on the END
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* ESB MMIO but our model only supports a single block per XIVE chip.
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*/
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end_blk = xive_router_get_block_id(xsrc->xrtr);
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end_idx = addr >> (xsrc->esb_shift + 1);
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if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
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@ -1855,7 +1867,6 @@ static void xive_end_source_realize(DeviceState *dev, Error **errp)
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}
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static Property xive_end_source_properties[] = {
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DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
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DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
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DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
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DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
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@ -351,6 +351,7 @@ typedef struct XiveRouterClass {
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XiveNVT *nvt);
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int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt, uint8_t word_number);
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uint8_t (*get_block_id)(XiveRouter *xrtr);
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} XiveRouterClass;
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int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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@ -431,7 +432,6 @@ typedef struct XiveENDSource {
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DeviceState parent;
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uint32_t nr_ends;
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uint8_t block_id;
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/* ESB memory region */
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uint32_t esb_shift;
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