target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. This allows us to add support for CPSR_DIT, adding helper functions to merge SPSR_ELx to and from CPSR. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -945,11 +945,31 @@ static int el_from_spsr(uint32_t spsr)
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}
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}
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static void cpsr_write_from_spsr_elx(CPUARMState *env,
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uint32_t val)
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{
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uint32_t mask;
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/* Save SPSR_ELx.SS into PSTATE. */
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env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS);
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val &= ~PSTATE_SS;
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/* Move DIT to the correct location for CPSR */
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if (val & PSTATE_DIT) {
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val &= ~PSTATE_DIT;
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val |= CPSR_DIT;
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}
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mask = aarch32_cpsr_valid_mask(env->features, \
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&env_archcpu(env)->isar);
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cpsr_write(env, val, mask, CPSRWriteRaw);
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}
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void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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{
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int cur_el = arm_current_el(env);
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unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
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uint32_t mask, spsr = env->banked_spsr[spsr_idx];
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uint32_t spsr = env->banked_spsr[spsr_idx];
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int new_el;
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bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
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@ -998,10 +1018,9 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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* will sort the register banks out for us, and we've already
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* caught all the bad-mode cases in el_from_spsr().
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*/
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mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
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cpsr_write(env, spsr, mask, CPSRWriteRaw);
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cpsr_write_from_spsr_elx(env, spsr);
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if (!arm_singlestep_active(env)) {
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env->uncached_cpsr &= ~PSTATE_SS;
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env->pstate &= ~PSTATE_SS;
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}
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aarch64_sync_64_to_32(env);
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@ -9445,7 +9445,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
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* For exceptions taken to AArch32 we must clear the SS bit in both
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* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
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*/
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env->uncached_cpsr &= ~PSTATE_SS;
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env->pstate &= ~PSTATE_SS;
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env->spsr = cpsr_read(env);
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/* Clear IT bits. */
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env->condexec_bits = 0;
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@ -9801,6 +9801,21 @@ static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
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}
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}
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static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
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{
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uint32_t ret = cpsr_read(env);
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/* Move DIT to the correct location for SPSR_ELx */
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if (ret & CPSR_DIT) {
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ret &= ~CPSR_DIT;
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ret |= PSTATE_DIT;
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}
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/* Merge PSTATE.SS into SPSR_ELx */
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ret |= env->pstate & PSTATE_SS;
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return ret;
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}
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/* Handle exception entry to a target EL which is using AArch64 */
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static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
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{
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@ -9923,7 +9938,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
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aarch64_save_sp(env, arm_current_el(env));
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env->elr_el[new_el] = env->pc;
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} else {
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old_mode = cpsr_read(env);
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old_mode = cpsr_read_for_spsr_elx(env);
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env->elr_el[new_el] = env->regs[15];
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aarch64_sync_32_to_64(env);
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@ -13217,7 +13232,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *pflags)
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{
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uint32_t flags = env->hflags;
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uint32_t pstate_for_ss;
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*cs_base = 0;
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assert_hflags_rebuild_correctly(env);
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@ -13227,7 +13241,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
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}
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pstate_for_ss = env->pstate;
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} else {
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*pc = env->regs[15];
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@ -13275,7 +13288,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
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flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
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pstate_for_ss = env->uncached_cpsr;
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}
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/*
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@ -13288,7 +13300,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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* SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
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*/
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if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
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(pstate_for_ss & PSTATE_SS)) {
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(env->pstate & PSTATE_SS)) {
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flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
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}
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@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
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uint32_t HELPER(cpsr_read)(CPUARMState *env)
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{
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/*
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* We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
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* This is convenient for populating SPSR_ELx, but must be
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* hidden from aarch32 mode, where it is not visible.
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*
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* TODO: ARMv8.4-DIT -- need to move SS somewhere else.
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*/
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return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
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return cpsr_read(env) & ~CPSR_EXEC;
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}
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void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
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