target/arm: Implement NSACR gating of floating point
The NSACR register allows secure code to configure the FPU to be inaccessible to non-secure code. If the NSACR.CP10 bit is set then: * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2) * CPACR.{CP10,CP11} behave as if RAZ/WI * HCPTR.{TCP11,TCP10} behave as if RAO/WI Note that we do not implement the NSACR.NSASEDIS bit which gates only access to Advanced SIMD, in the same way that we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190510110357.18825-1-peter.maydell@linaro.org
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@ -930,9 +930,36 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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}
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value &= mask;
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value &= mask;
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}
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}
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/*
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* For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
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* is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
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*/
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
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!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
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value &= ~(0xf << 20);
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value |= env->cp15.cpacr_el1 & (0xf << 20);
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}
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env->cp15.cpacr_el1 = value;
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env->cp15.cpacr_el1 = value;
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}
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}
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static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/*
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* For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
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* is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
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*/
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uint64_t value = env->cp15.cpacr_el1;
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
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!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
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value &= ~(0xf << 20);
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}
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return value;
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}
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static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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{
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/* Call cpacr_write() so that we reset with the correct RAO bits set
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/* Call cpacr_write() so that we reset with the correct RAO bits set
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@ -998,7 +1025,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
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{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
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.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
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.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
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.resetfn = cpacr_reset, .writefn = cpacr_write },
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.resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -4683,6 +4710,36 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
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return ret;
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return ret;
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}
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}
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static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* For A-profile AArch32 EL3, if NSACR.CP10
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* is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
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*/
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
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!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
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value &= ~(0x3 << 10);
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value |= env->cp15.cptr_el[2] & (0x3 << 10);
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}
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env->cp15.cptr_el[2] = value;
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}
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static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/*
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* For A-profile AArch32 EL3, if NSACR.CP10
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* is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
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*/
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uint64_t value = env->cp15.cptr_el[2];
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
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!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
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value |= 0x3 << 10;
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}
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return value;
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}
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static const ARMCPRegInfo el2_cp_reginfo[] = {
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static const ARMCPRegInfo el2_cp_reginfo[] = {
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{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
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{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_IO,
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.type = ARM_CP_IO,
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@ -4730,7 +4787,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
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{ .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
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{ .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
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.access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
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.access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
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.fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]),
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.readfn = cptr_el2_read, .writefn = cptr_el2_write },
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{ .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
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{ .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
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.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
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.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
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@ -13587,6 +13645,19 @@ int fp_exception_el(CPUARMState *env, int cur_el)
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break;
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break;
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}
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}
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/*
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* The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
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* to control non-secure access to the FPU. It doesn't have any
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* effect if EL3 is AArch64 or if EL3 doesn't exist at all.
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*/
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if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
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cur_el <= 2 && !arm_is_secure_below_el3(env))) {
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if (!extract32(env->cp15.nsacr, 10, 1)) {
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/* FP insns act as UNDEF */
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return cur_el == 2 ? 2 : 1;
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}
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}
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/* For the CPTR registers we don't need to guard with an ARM_FEATURE
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/* For the CPTR registers we don't need to guard with an ARM_FEATURE
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* check because zero bits in the registers mean "don't trap".
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* check because zero bits in the registers mean "don't trap".
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*/
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*/
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