Commit graph

30879 commits

Author SHA1 Message Date
Peter Maydell 60510aed69 target-arm: A64: Implement unprivileged load/store
Implement the unprivileged load and store instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:56 +00:00
Peter Maydell e4b998d47d target-arm: A64: Implement narrowing three-reg-diff operations
Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:56 +00:00
Peter Maydell dfc15c7ceb target-arm: A64: Implement the wide 3-reg-different operations
Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:56 +00:00
Peter Maydell 70d7f984a0 target-arm: A64: Add most remaining three-reg-diff widening ops
Add the remainder of the 64x64->128 operations in the three-reg-diff
category except for PMULL, PMULL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:55 +00:00
Peter Maydell 13caf1fd2b target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:55 +00:00
Peter Maydell d324b36ad9 target-arm: A64: Implement store-exclusive for system mode
System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:55 +00:00
Peter Maydell 7900e9f1f9 target-arm: Fix incorrect type for value argument to write_raw_cp_reg
The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:54 +00:00
Peter Maydell 59a1c327d7 target-arm: Remove failure status return from read/write_raw_cp_reg
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:54 +00:00
Peter Maydell ea4571eb87 target-arm: Remove unnecessary code now read/write fns can't fail
Now that cpreg read and write functions can't fail and throw an
exception, we can remove the code from the translator that synchronises
the guest PC in case an exception is thrown.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:54 +00:00
Peter Maydell c4241c7d38 target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean up
their prototypes:
 * write functions return void
 * read functions return the value rather than taking a pointer
   to write the value to

This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:54 +00:00
Peter Maydell 92611c0019 target-arm: Convert miscellaneous reginfo structs to accessfn
Convert the remaining miscellaneous cases of reginfo read/write
functions returning EXCP_UDEF to use an accessfn instead:
TEEHBR, and the ATS address-translation operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:53 +00:00
Peter Maydell 00108f2d4d target-arm: Convert generic timer reginfo to accessfn
Convert the reginfo structs for the generic timer registers
to use access functions rather than returning EXCP_UDEF from
their read handlers. In some cases this allows us to remove
a read handler completely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:53 +00:00
Peter Maydell fcd252062a target-arm: Convert performance monitor reginfo to accessfn
Convert the performance monitor reginfo definitions to use
an accessfn rather than returning EXCP_UDEF from read and
write functions. This also allows us to fix a couple of XXX
cases where we weren't imposing the access restrictions on
RAZ/WI or constant registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:52 +00:00
Peter Maydell f59df3f235 target-arm: Split cpreg access checks out from read/write functions
Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedicated
"check access rights" function pointer in the ARMCPRegInfo.
This will allow us to simplify some of the register definitions,
which no longer need read/write functions purely to handle
the access checks.

We take the opportunity to define the return value from the
access checking function in a way that allows us to set the
correct exception syndrome information for exceptions taken
to AArch64 (which may need to distinguish access failures due
to a configurable trap or enable from other kinds of access
failure).

This commit defines the new mechanism but does not move any
of the registers across to use it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:52 +00:00
Peter Maydell e508a92b62 target-arm: Stop underdecoding ARM946 PRBS registers
The ARM946 has 8 PRBS (protection region base and size) registers.
Currently we implement these with a CP_ANY reginfo; however this
underdecodes (since there are 16 possible values of CRm but only
8 registers) and we catch the invalid values in the read and
write functions. However this causes issues with migration since
we only migrate the first of a wildcard register set, so we only
migrate c6_region[0]. It also makes it awkward to pull reginfo
access checks out into their own function.

Avoid all these problems by just defining separate reginfo structs
for each of the 8 registers; this also lets us avoid having any
read or write functions and will result in more efficient direct
field accesses from generated code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:52 +00:00
Peter Maydell 626187d86b target-arm: Log bad system register accesses with LOG_UNIMP
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:52 +00:00
Peter Maydell 1456364ff0 target-arm: Remove unused ARMCPUState sr substruct
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:51 +00:00
Peter Maydell 99f678a679 target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20 10:35:51 +00:00
Peter Maydell 76e3e1bcae target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:51 +00:00
Peter Maydell 83e9a4aec9 target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20 10:35:50 +00:00
Peter Maydell 057d5f62f8 target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-same
and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,
FACGT, FMLA and FMLS.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:50 +00:00
Peter Maydell 67d43538ae softfloat: Support halving the result of muladd operation
The ARMv8 instruction set includes a fused floating point
reciprocal square root step instruction which demands an
"(x * y + z) / 2" fused operation. Support this by adding
a flag to the softfloat muladd operations which requests
that the result is halved before rounding.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:50 +00:00
Alex Bennée bc242f9bb6 target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:50 +00:00
Alex Bennée 8908f4d185 target-arm: A64: Implement SIMD FP compare and set insns
This adds all forms of the SIMD floating point and set instructions:

  FCM(GT|GE|EQ|LE|LT)

Most of the heavy lifting is done by either the existing neon helpers or
some new helpers for the 64bit double cases. Most of the code paths are
common although the 2misc versions are a little special as they compare
against zero.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[PMM: fixed some minor bugs, added the 2-misc-scalar encoding]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:49 +00:00
Peter Maydell b033cd3d00 target-arm: A64: Implement scalar three different instructions
Implement the scalar three different instruction group:
it only has three instructions in it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:49 +00:00
Peter Maydell 9f82e0ff4b target-arm: A64: Implement SIMD scalar indexed instructions
Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:49 +00:00
Peter Maydell c44ad1fddc target-arm: A64: Implement long vector x indexed insns
Implement the 'long' operations in the vector x indexed
element category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:49 +00:00
Peter Maydell f5e51e7f10 target-arm: A64: Implement plain vector SIMD indexed element insns
Implement all the SIMD vector x indexed element instructions
in the subcategory which are not 'long' ops.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:48 +00:00
Peter Maydell 873169022a hw/intc/arm_gic: Fix NVIC assertion failure
Commit 40d225009e accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
  gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed.

Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2014-02-20 10:35:48 +00:00
Brad 46eef33b89 Fix QEMU build on OpenBSD on x86 archs
This resolves the build issue with building the ROMs on OpenBSD on x86 archs.
As of OpenBSD 5.3 the compiler builds PIE binaries by default and thus the
whole OS/packages and so forth. The ROMs need to have PIE disabled.
Check in configure whether the compiler supports the flags for disabling
PIE, and if it does then use them for building the ROMs. This fixes the
following buildbot failure:

>From the OpenBSD buildbots..
  Building optionrom/multiboot.img
ld: multiboot.o: relocation R_X86_64_16 can not be used when making a shared object; recompile with -fPIC

Signed-off by: Brad Smith <brad@comstyle.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-17 11:44:00 +00:00
Michael Tokarev 0dbcf95a1e libvixl: fix 64bit constants usage
Since commit 999b53ec8794f203964db3ecf939a3da5c4bc843:
 Author: Claudio Fontana <claudio.fontana@linaro.org>
 Date:   Wed Feb 5 17:27:28 2014 +0000

    disas: Implement disassembly output for A64

    Use libvixl to implement disassembly output in debug
    logs for A64, for use with both AArch64 hosts and targets.

disas/libvixl/ contains functions which uses 64bit constants
without using appropriate suffixes, which fails on 32bits.

Fix this by using ULL suffix.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 20:26:30 +00:00
Peter Maydell 078a1c37ca trivial patches for 2014-02-15
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Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-02-15' into staging

trivial patches for 2014-02-15

# gpg: Signature made Sat 15 Feb 2014 12:10:46 GMT using RSA key ID 74F0C838
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: E190 8639 3B10 B51B AC2C  8B73 5253 C5AD 74F0 C838

* remotes/mjt/tags/trivial-patches-2014-02-15:
  char/serial: Fix emptyness check
  gitignore: anchor all ignored names
  vl: trim includes
  vl: remove old, long-unused defines
  net: declare struct iovec in checksum.h to fix compiler warning
  linux-user: refactor do_socketcall()
  configure: add hints to a remedy for feature_not_found errors
  configure: add hint of libfdt to DTC dependency not found message
  sparc/leon3: Initialize stack pointer
  misc: Fix case Qemu -> QEMU

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 16:36:40 +00:00
Peter Maydell 44e3a39f30 Block pull request
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Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

Block pull request

# gpg: Signature made Fri 14 Feb 2014 17:26:30 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/block-pull-request:
  block: Open by reference will try device then node_name.
  block: Relax bdrv_lookup_bs constraints.
  blockdev: Fix wrong usage of QDECREF causing snapshoted quorum to crash on close.
  block: mirror - use local_err to avoid NULL errp
  qemu-iotests: Don't run 005 on vmdk split formats
  block: qemu-iotests - add vhdx log replay tests for qemu-img
  block: qemu-iotests - fix test 070 (vhdx)
  block: Don't throw away errno via error_setg
  block: Add notes to iSCSI's .bdrv_open and .bdrv_reopen_prepare
  blockdev: Remove 'type' parameter from blockdev_init()
  sdhci: Drop unnecessary #include

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 16:15:52 +00:00
Peter Maydell 90ce3d76eb Merge remote-tracking branch 'remotes/jliu/or32-ld-st' into staging
* remotes/jliu/or32-ld-st:
  target-openrisc: Use new qemu_ld/st opcodes

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 15:20:08 +00:00
Peter Maydell a50f98b066 Merge remote-tracking branch 'remotes/jovanovic/mips-ufrp' into staging
* remotes/jovanovic/mips-ufrp:
  target-mips: add user-mode FR switch support for MIPS32r5
  target-mips: add support for CP0_Config5
  target-mips: add support for CP0_Config4
  target-mips: add CPU definition for MIPS32R5

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 15:07:00 +00:00
Peter Crosthwaite 88c1ee73d3 char/serial: Fix emptyness check
This was guarding against a full fifo rather than an empty fifo when
popping. Fix.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Martin Kletzander <mkletzan@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Michael Tokarev 5556332aba gitignore: anchor all ignored names
by default, patterns/names in .gitignore are applied
recursively to all subdirectories.  So any name mentioned
in .gitignore is ignored in all subdirectores.  This is good
for, say. object files (*.o), but not good for particular
names which should be ignored only in one directory.  For
example, qemu-img.1 file is generated in the top directory,
and it should be ignored only there, not in some subdir.

At first, this might not matter much, but we have lots of
examples already where it actually does not help at all.
For example, top-level .gitignore ignores a file/dir named
"patches" (which is very questionable by itself), but it
is applied recursively, so git also ignores, for example,
debian/patches/ which should not be ignored.

So anchor all the names where appropriate.  .gitignore
should be cleaned up further, which will be addressed in
a subsequent patch.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Michael Tokarev b33276a7a8 vl: trim includes
Over time, lots of stuff moved from vl.c into separate
files.  But include statements has never been cleaned,
and they continue to carry lots of anymore-unused stuff.

Remove includes which are not relevant for vl.c anymore.
Apparently there are more includes like this, because
many are included from qemu-common.h and the like, or,
for example, I don't see were we use win32-specific
stuff in vl.c (so that maybe #include <windows.h> might
be removed too).

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Michael Tokarev 24c84e687e vl: remove old, long-unused defines
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Michael Tokarev 262471794d net: declare struct iovec in checksum.h to fix compiler warning
The checksum calculation header exports a function that refers to
struct iov defined in iov.h.  Without including the former, build
fails like this:

  In file included from hw/net/fsl_etsec/rings.c:24:0:
  include/net/checksum.h:51:31: error: ‘struct iovec’ declared inside parameter list [-Werror]
  include/net/checksum.h:51:31: error: its scope is only this definition or declaration, which is probably not what you want [-Werror]

Mention struct iovec there.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Michael Tokarev 62dc90c668 linux-user: refactor do_socketcall()
Refactor do_socketcall() to do argument conversion/checking first,
according to a lookup table (which call has how many args) and
by calling the right function second with ready-to-go arguments.

This ensures that all arguments are handled as abi_long, according
to socketcall prototype, and simplifies argument handling alot too.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-15 16:10:25 +04:00
Stewart Smith 21684af023 configure: add hints to a remedy for feature_not_found errors
Modify feature_not_found to accept an optional second parameter to be
printed after the generic feature not found error.

Modify most calls to feature_not_found to provide hints as to the
packages that may be missing. The few calls remaining without a remedy
are ones I couldn't work out how to remedy myself.

Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Stewart Smith 3f281822b2 configure: add hint of libfdt to DTC dependency not found message
Most distros package it as libfdt, and mentioning libfdt here makes it
much easier to find the package you're missing.

Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Sebastian Huber c1570e2a1f sparc/leon3: Initialize stack pointer
A lot of real world LEON3 systems are shipped with the GRMON boot
loader.  This boot loader initializes the stack pointer with the end of
RAM address.  The application can use this to detect the RAM size of a
particular board variant.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Stefan Weil a63e5e0c0d misc: Fix case Qemu -> QEMU
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-15 16:10:25 +04:00
Benoît Canet 0c5e94ee83 block: Open by reference will try device then node_name.
Since we introduced node_name for named bs of the graph modify the opening by
reference to use it as a fallback.

This patch also enforce the separation of the device id and graph node
namespaces.

Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-02-14 18:05:39 +01:00
Benoît Canet dd67fa5052 block: Relax bdrv_lookup_bs constraints.
The following patch will reuse bdrv_lookup_bs in order to open images by
references so the rules of usage of bdrv_lookup_bs must be relaxed a bit.

Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-02-14 18:05:39 +01:00
Benoît Canet 57b6bdf37c blockdev: Fix wrong usage of QDECREF causing snapshoted quorum to crash on close.
As bdrv_open() documentation states:
"The reference to the QDict belongs to the block layer
 * after the call (even on failure), so if the caller intends to reuse the
 * dictionary, it needs to use QINCREF() before calling bdrv_open."

the optional options dict will not be reused after bdrv_open() and should
belong to the block layer so remove the extra QDECREF(options).

Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-02-14 18:05:39 +01:00
Jeff Cody cc67f4d1f9 block: mirror - use local_err to avoid NULL errp
When starting a block job, commit_active_start() relies on whether *errp
is set by mirror_start_job.  This allows it to determine if the mirror
job start failed, so that it can clean up any changes to open flags from
the bdrv_reopen().  If errp is NULL, then it will not be able to
determine if mirror_start_job failed or not.

To avoid this, use a local Error variable, and then propagate the error
(if any) to errp.

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Jeff Cody <jcody@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-02-14 18:05:39 +01:00
Fam Zheng 2aa4a86f59 qemu-iotests: Don't run 005 on vmdk split formats
There would be too many extents that VMDK driver can't open all of them:

    005 0s ... - output mismatch (see 005.out.bad)
    --- 005.out     2013-12-24 09:27:27.608181030 +0800
    +++ 005.out.bad 2014-02-13 10:00:15.282184557 +0800
    @@ -4,10 +4,10 @@
     Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=5368709120000

     small read
    -read 4096/4096 bytes at offset 1024
    -4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
    +qemu-io: can't open device /tmp/qemu-iotests/t.vmdk: Could not open '/tmp/qemu-iotests/t-s1016.vmdk': Too many open files
    +no file open, try 'help open'

     small write
    -wrote 4096/4096 bytes at offset 8192
    -4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
    +qemu-io: can't open device /tmp/qemu-iotests/t.vmdk: Could not open '/tmp/qemu-iotests/t-s1016.vmdk': Too many open files
    +no file open, try 'help open'
     *** done

So disable the two subformats.

Signed-off-by: Fam Zheng <famz@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-02-14 18:05:39 +01:00