aurel32
d445bde7e8
target-ppc: remove dead code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6055 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:58 +00:00
aurel32
196e3422f7
target-ppc: enable PRECISE_EMULATION by default
...
With this option enabled, all glibc math tests pass.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6054 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:50 +00:00
aurel32
da1e7ac9d4
target-ppc: fmadd/fmsub/fmnadd/fmnsub can generate VXIMZ or VXIZI exceptions
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6053 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:43 +00:00
aurel32
17218d1fd9
target-ppc: fadd/fsub: correctly propagate NaN
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6052 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:35 +00:00
aurel32
f23c346e69
target-ppc: use the new fp functions
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6051 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:27 +00:00
aurel32
3b27fc36e3
target-ppc: correctly propagate NaN in division
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6048 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:14:05 +00:00
aurel32
e0147e4138
target-ppc: fix fload_invalid_op_excp()
...
The argument is a value, not a flag. Update the tests accordingly. Also
set a correct default value for NaN.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6047 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:13:55 +00:00
aurel32
05b936038f
target-ppc: use a correct value to represent 1.0
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6046 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:13:48 +00:00
aurel32
eb44b959de
target-ppc: update nip before calling an helper in FP instructions
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6045 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:13:39 +00:00
aurel32
330c483bbf
target-ppc: fix TCGv type in fcmpu/fcmpo
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6044 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 17:13:31 +00:00
aurel32
ab5f265daa
target-ppc: add signed fields to ppc_avr_t.
...
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6042 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 07:03:06 +00:00
aurel32
6ad193ed43
target-ppc: fix frsp instruction
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6036 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 01:00:17 +00:00
aurel32
27ee5df007
target-ppc: fix mtfsf and mtfsfi instructions
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6035 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 00:30:28 +00:00
aurel32
9a819377d8
target-ppc: fix fcmp{o,u} instructions
...
The instructions are specified to update the condition register even if
an error is to be signaled because of NaN input.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6034 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 19:34:09 +00:00
aurel32
b12363e1b7
target-ppc: remove FPRF optimization
...
FPRF optimization is totally broken, remove it.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6033 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 18:59:08 +00:00
aurel32
6e35d5243c
target-ppc: fix mtfsb0 and mtfsb1
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6032 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 18:40:58 +00:00
aurel32
7889270acb
target-ppc: display FPSCR in register dump
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6031 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 18:40:49 +00:00
aurel32
2637004698
target-ppc: fix mbar opcode
...
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6027 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 11:12:20 +00:00
aurel32
6ad7365a81
target-ppc: fix fsel instruction
...
Fix fsel instruction. Eliminate unneeded temporaries while we're at it,
too.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6026 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-14 11:12:10 +00:00
aurel32
5e9ae189f8
target-ppc: keep only the table version for mfrom
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6007 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 12:30:21 +00:00
aurel32
be94c952e4
target-ppc: use accessors to access fp_status exception_flags
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6006 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 12:13:33 +00:00
aurel32
cf1cf21eac
target-ppc: fix compilation with PRECISE_EMULATION
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6004 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 11:46:36 +00:00
aurel32
a44d2ce18a
target-ppc: fix compilation with CONFIG_SOFTFLOAT
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6003 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 11:46:27 +00:00
aurel32
9322057384
target-ppc: remove remaining warnings
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:33 +00:00
aurel32
94fa46e2c2
target-ppc: remove unneeded include
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5990 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:25 +00:00
aurel32
e06fcd754e
target-ppc: rework exception code
...
... also remove two warnings.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:14 +00:00
aurel32
2a3ec4b5b3
target-ppc: remove dead code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5988 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:04 +00:00
aurel32
4c2ab98869
target-ppc: enable SPE and Altivec in user mode
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5965 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:02:33 +00:00
aurel32
fe463b7dbc
target-ppc: initialize MSR appropriately in user-mode
...
Mask the initial MSR with the mask from the PowerPC CPU definition.
Noticed by Nathan Froyd.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:02:24 +00:00
aurel32
db9a16a70c
target-ppc: kill a warning
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5952 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-08 18:11:50 +00:00
aurel32
0e69805af6
target-ppc: cleanup op_helper.c after TCG conversion
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5951 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-08 18:11:42 +00:00
aurel32
b4cec7b455
target-ppc: enable access type in MMU
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5950 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-08 18:11:33 +00:00
aurel32
76db3ba44e
target-ppc: memory load/store rework
...
Rework the memory load/store:
- Unify load/store functions for 32-bit and 64-bit CPU
- Don't swap values twice for bit-reverse load/store functions
in little endian mode.
- On a 64-bit CPU in 32-bit mode, do the address truncation for
address computation instead of every load store. Truncate the
address when incrementing the address (if needed)
- Cache writes to access_types.
- Add a few missing calls to gen_set_access_type()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5949 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-08 18:11:21 +00:00
aurel32
0c34a5d722
target-ppc: kill a few warnings
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:00:00 +00:00
aurel32
e8fc4fa7a1
target-ppc: disable single stepping
...
... which left was enabled by mistake.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5918 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 16:23:22 +00:00
aurel32
ec72e276c5
target-ppc: Fix use of uninitialized TCG variable in tlbiva
...
Silences a warning about possible unitialized use of t0.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5915 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 15:45:15 +00:00
aurel32
45d827d2d7
target-ppc: convert SPR accesses to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 13:40:29 +00:00
aurel32
fa0d32c4e4
target-ppc: remove dead code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5909 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 13:40:15 +00:00
aurel32
8983da70c4
target-ppc: remove dead code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 22:01:01 +00:00
aurel32
74d37793f4
target-ppc: convert SLB/TLB instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 21:46:17 +00:00
aurel32
06dca6a7c1
target-ppc: convert dcr load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 16:37:18 +00:00
aurel32
6527f6ea9c
target-ppc: convert msr load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 13:03:35 +00:00
aurel32
22e0e17337
target-ppc: convert POWER bridge instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 12:19:14 +00:00
aurel32
7487953d70
target-ppc: convert POWER shift instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5882 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-05 07:21:44 +00:00
aurel32
54cdcae646
target-ppc: add functions to load/store SPR
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5881 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-05 07:21:31 +00:00
aurel32
b8dbdddc9e
target-ppc: remove unused file op_mem_access.h
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5838 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 17:54:28 +00:00
aurel32
dcc532c809
target-ppc: use ldl/ldub/stl/stub for load/store in op_helper.c
...
Should not give any performance penality given cpu_mmu_index() is
an inline function returning a value from env.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5837 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 17:54:21 +00:00
aurel32
ef0d51af1e
target-ppc: convert PPC 440 instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 17:26:29 +00:00
aurel32
d72a19f7bd
target-ppc: convert return from interrupt instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:55 +00:00
aurel32
fa407c030c
target-ppc: convert external load/store instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5831 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:47 +00:00
aurel32
cf360a32af
target-ppc: convert load/store with reservation instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5830 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:39 +00:00
aurel32
bdb4b68907
target-ppc: convert lscbx instruction to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:30 +00:00
aurel32
dfbc799d8e
target-ppc: convert load/store string instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:21 +00:00
aurel32
37d269dfc6
target-ppc: convert icbi instruction to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:13 +00:00
aurel32
799a8c8d0a
target-ppc: convert dcbz instruction to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:24:05 +00:00
aurel32
ff4a62cd81
target-ppc: convert load/store multiple instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:56 +00:00
aurel32
931ff27258
target-ppc: convert wait instruction to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5824 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:46 +00:00
aurel32
cf02a65c77
target-ppc: convert mfrom instruction to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5823 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:35 +00:00
aurel32
e49a3c8f85
target-ppc: remove dead code from op.c
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5822 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:25 +00:00
aurel32
2cbd949d7a
Common cpu_loop_exit prototype
...
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:09 +00:00
aurel32
0f3955e2d2
target-ppc: convert software TLB instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5819 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:22:56 +00:00
aurel32
01a4afeb99
target-ppc: convert POWER2 load/store instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27 19:30:56 +00:00
aurel32
6a6ae23f3c
target-ppc: convert SPE load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27 19:30:47 +00:00
aurel32
38d1495201
target-ppc: simplify evsplati and evsplatfi
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5803 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27 19:30:38 +00:00
aliguori
c0ce998e94
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
...
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 22:13:57 +00:00
aurel32
cab3bee2d6
target-ppc: convert trap instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-24 11:28:19 +00:00
aurel32
fe1e5c53fd
target-ppc: convert altivec load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-24 08:47:21 +00:00
aurel32
a0d7d5a776
target-ppc: convert FPU load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5786 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23 16:30:50 +00:00
aurel32
a7859e892b
target-ppc: fix access_type usage
...
Write env->access_type before a load/store operation instead of relying
on the name of the dyngen operation.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5785 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23 16:30:40 +00:00
aurel32
0c8aacd466
target-ppc: include the instruction name in load/store handlers name
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5784 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23 16:30:28 +00:00
aurel32
1c97856dcc
target-ppc: convert SPE FP ops to TCG
...
Including a few bug fixes:
- Don't clear high part for instruction with 32-bit destination
- Fix efscmp* and etstcmp* return value
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5783 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23 10:54:04 +00:00
aurel32
293d6942dd
target-ppc: remove declaration of removed function from op_helper.h
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5781 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22 21:27:36 +00:00
aurel32
64adab3fcb
target-ppc: convert exceptions generation to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22 10:09:17 +00:00
aurel32
0f2f39c234
target-ppc: fix TCG type errors introduced in r5754
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5756 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19 17:54:49 +00:00
aurel32
af12906f77
target-ppc: convert fp ops to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19 16:10:23 +00:00
aliguori
a1d1bb3101
Refactor and enhance break/watchpoint API (Jan Kiszka)
...
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.
Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:07:32 +00:00
aliguori
6b9175478e
Refactor translation block CPU state handling (Jan Kiszka)
...
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori
622ed3605b
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
...
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
aurel32
87006d1378
target-ppc: fix regression introduced by commit 5729
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5733 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 09:32:01 +00:00
pbrook
a7812ae412
TCG variable type checking.
...
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
blueswir1
cd390083ad
Attached patch fixes a series of this warning
...
when compiling on NetBSD:
warning: array subscript has type 'char'
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5727 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-16 13:53:32 +00:00
aurel32
57951c2742
target-ppc: convert most SPE integer instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-10 11:10:23 +00:00
aurel32
741a7444a3
target-ppc: fix TCG argument
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5661 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 18:27:28 +00:00
aurel32
a973001797
target-ppc: Remove a few TCG temp variable leaks
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5660 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 17:27:36 +00:00
aurel32
ec6469a3b1
target-ppc: fixes for gen_op_neg()
...
- Rename to gen_op_arith_neg for consistency with other functions.
- Correctly free TCG temp variable.
- Fix the return value in 64-bit mode in case of overflow.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 17:27:27 +00:00
aurel32
2ef1b120d1
target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes
...
gen_op_arith_divw():
- "deoptimize" gen_op_arith_divw to make it more readable.
- Correctly free TCG temp variable
gen_op_arith_divd():
- Call the right function.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5658 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 17:27:19 +00:00
aurel32
1e4c090f7d
target-ppc: optimize mullw and make the code more readable
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 17:27:11 +00:00
aurel32
bdc4e053d1
target-ppc: indentation fixes
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5656 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-09 17:27:03 +00:00
aurel32
4870167d04
target-ppc: fix tcg fatal error on i386 host
...
It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.
Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5648 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-08 08:57:45 +00:00
aurel32
e32ad5c268
target-ppc: fix flags computation for tcg_gen_qemu_st
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5644 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-07 13:48:25 +00:00
aurel32
54843a5861
target-ppc: use the new rotr/rotri instructions
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-03 07:08:44 +00:00
aurel32
fdce4963ea
target-ppc: use the new subfi wrapper
...
(...and fix rldnm)
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5600 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-02 08:23:14 +00:00
aurel32
0cfe58cd44
target-ppc: simplify slw, srw, sld, srd
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5597 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-02 08:22:45 +00:00
aurel32
fea0c503a0
target-ppc: be more consistent with temp variables naming
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5596 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-02 08:22:34 +00:00
aurel32
4da0033e6e
target-ppc: fix srw on 64-bit targets
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-02 08:22:16 +00:00
aurel32
6176a26d1d
target-ppc: optimize popcntb
...
Suggested by Andrzej Zaborowski.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5592 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:54:33 +00:00
aurel32
182608d44c
target-ppc: convert 405 MAC instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5591 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:54:23 +00:00
aurel32
7463740644
target-ppc: convert arithmetic functions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:54:12 +00:00
aurel32
8d71247eaa
target-ppc: xer access prototypes no more used & implemented
...
Revision 5500 of the qemu repository removed all code using
ppc_load_xer & ppc_store_xer as well as their implementation.
Another patch fixes it's usage in kvm-userspace for powerpc, but I think
that header can now be cleaned up, therefore this patch to qemu-devel.
Signed-off-by: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5589 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:53:59 +00:00
aurel32
269f3e95e8
target-ppc: fix XER accesses on 64-bit targets
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5588 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01 00:53:48 +00:00
aurel32
ea36369470
target-ppc: use consistent names for variables
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5557 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-27 22:50:39 +00:00
aurel32
312179c419
target-ppc: indentation fixes
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5556 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-27 22:50:31 +00:00
aurel32
d03ef5116b
target-ppc: convert rotation instructions to TCG
...
Also fix rlwimi and rldimi for corner cases.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5555 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-27 22:50:22 +00:00
pbrook
2e31f5d38c
Fix typos in PPC TCG conversion.
...
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5521 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-24 12:03:16 +00:00
aurel32
a2ffb81204
target-ppc: convert branch related instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5508 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 16:31:31 +00:00
aurel32
26d6736245
target-ppc: convert logical instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:31:27 +00:00
aurel32
e1571908a2
target-ppc: convert crf related instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:31:14 +00:00
aurel32
cf960816f9
target-ppc: use the new TCG logical operations
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5503 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:29:55 +00:00
aurel32
3d7b417e13
target-ppc: Convert XER accesses to TCG
...
Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21 11:28:46 +00:00
aurel32
ed69522caf
PPC: fix dcbi instruction
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5495 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15 22:25:21 +00:00
aurel32
3d3a6a0a48
PPC: convert SPE logical instructions to TCG
...
(Nathan Froyd)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15 17:00:45 +00:00
aurel32
b61f2753a7
ppc: convert integer load/store to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5493 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15 17:00:37 +00:00
aurel32
19f98ff634
target-ppc: fix a TCG local variable creation
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5492 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15 17:00:29 +00:00
aurel32
f0aabd1aa3
PPC: convert SPE effective address computation to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15 17:00:18 +00:00
aurel32
e2be8d8d7e
PPC: convert effective address computation to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-14 19:55:54 +00:00
aurel32
ee600be6a6
ppc: fix crash in ppc system single step support
...
There was a bogus case where two system debug ops get generated. This
patch removes the broken system debug op. This was a left over after
making some changes to correctly generate debug ops on branch
operations inside gen_goto_tb();
The test case against this patch is to turn on single stepping with
timers, boot a linux kernel, set a breakpoint a do_fork and in gdb
execute "si 3000". Then qemu-system-ppc will fault executing a debug
op, which should not have been executed.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5391 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01 22:01:37 +00:00
aurel32
0cadcbbe65
target-ppc: fix computation of XER.{CA, OV} in addme, subfme
...
(Jocelyn Mayer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5380 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01 21:45:37 +00:00
aurel32
5bf06a9528
target-ppc: fix mullw/mullwo
...
Based on patch by Julian Seward.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5379 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01 21:45:18 +00:00
pbrook
36aa55dcd9
Add concat_i32_i64 op.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 13:48:32 +00:00
blueswir1
b55266b5a2
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20 08:07:15 +00:00
aurel32
0df5bdbe0f
ppc: Convert op_andi to TCG
...
Replace op_andi_... with tcg_gen_andi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5218 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 18:30:32 +00:00
aurel32
cfdcd37aa5
ppc: Convert ctr, lr moves to TCG
...
Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr}
with tcg_gen_mov_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 18:30:23 +00:00
aurel32
7c417963f7
ppc: Convert op_subf to TCG
...
Replace op_subf with tcg_gen_sub_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:51 +00:00
aurel32
39dd32eed2
ppc: Convert op_add, op_addi to TCG
...
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:43 +00:00
aurel32
489251fa54
ppc: replace op_set_FT0 with tcg_gen_movi_i64
...
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 20:34:31 +00:00
aurel32
bd568f1849
ppc: Convert nip moves to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 18:06:03 +00:00
aurel32
d38ff48941
ppc: remove unused code
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:16:41 +00:00
aurel32
47e4661cc4
ppc: Convert CRF moves to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 17:06:47 +00:00
aurel32
ec1ac72d9c
ppc: fix fpr TCG registers creation
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 15:49:12 +00:00
aurel32
a5e26afa61
ppc: Convert FPR moves to TCG
...
Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].
This obsoletes op_template.h for REG > 7.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:54 +00:00
aurel32
1d54269590
ppc: Convert Altivec register moves to TCG
...
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 14:43:45 +00:00
aurel32
bd7d9a6d7b
ppc: cleanup register types
...
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:26:09 +00:00
aurel32
f78fb44e82
ppc: Convert GPR moves to TCG
...
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].
For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04 05:25:47 +00:00
aurel32
f0413473ff
[ppc] Convert op_moven_T2_T0 to TCG
...
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:40 +00:00
aurel32
86c581dc80
[ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG
...
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 23:26:32 +00:00
aurel32
e55fd9340e
[ppc] Convert op_move_{T1,T2}_T0 to TCG
...
Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with
tcg_gen_mov_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:19:05 +00:00
aurel32
02f4f6c24c
[ppc] Convert gen_set_{T0,T1} to TCG
...
The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:55 +00:00
blueswir1
79383c9c08
Fix some warnings that would be generated by gcc -Wredundant-decls
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 09:51:20 +00:00
aurel32
f10dc08e00
PPC: add support for TCG helpers
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5094 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-28 21:01:45 +00:00
aurel32
1c73fe5bba
PPC: Init TCG variables
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5093 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-28 21:01:36 +00:00
aurel32
6676f42453
Revert commits 5082 and 5083
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5084 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24 23:16:35 +00:00
aurel32
61c0480722
PPC: Switch a few instructions to TCG
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24 19:05:35 +00:00
aurel32
c0692e3c65
PPC: Init TCG variables
...
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5082 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24 19:05:26 +00:00
ths
9ceb2a77ad
Fix encoding of efsctsiz (powerpc spe), by Tristan Gingold.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4999 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-13 11:30:10 +00:00
ths
2cfc5f17d3
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18 18:01:29 +00:00
pbrook
9656f324d2
Move interrupt_request and user_mode_only to common cpu state.
...
Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 20:01:19 +00:00
pbrook
b3c7724cbc
Move CPU save/load registration to common code.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 16:31:04 +00:00
pbrook
b2437bf267
Add missing static qualifiers.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 12:29:56 +00:00
pbrook
2e70f6efa8
Add instruction counter.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
aurel32
e4bb997e06
PPC: fix mtfsfi
...
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4748 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-18 22:10:12 +00:00
ths
1235fc066a
Spelling fixes, by Stefan Weil.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-03 19:51:57 +00:00
pbrook
f8ed7070ea
Fix typo.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:54:15 +00:00
pbrook
6e68e076e7
Move clone() register setup to target specific code. Handle fork-like clone.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:22:15 +00:00
bellard
9133e39b84
Push common interrupt variables to cpu-defs.h (Glauber Costa)
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 10:08:06 +00:00
bellard
ce5232c5c2
moved halted field to CPU_COMMON
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 17:14:10 +00:00
pbrook
9b7b85d260
Fix off-by-one unwinding error.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25 00:36:06 +00:00
aurel32
8cbcb4fa2c
Fix broken PPC user space single stepping
...
(Jason Wessel)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4421 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-10 23:28:14 +00:00
aurel32
894efddb50
PPC: fix efstst* instructions
...
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4362 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 14:58:23 +00:00
aurel32
f9320410e1
PPC: fix definition of msr_spe
...
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4361 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 14:58:15 +00:00
aurel32
fd501a05c6
PPC: fix isel opcode decoding
...
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4345 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-05 21:27:18 +00:00
aurel32
8dd3dca351
remove target ifdefs from vl.c
...
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04 13:11:44 +00:00
aurel32
d2856f1ad4
Factorize code in translate.c
...
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-28 00:32:32 +00:00
aurel32
ca10f86763
Remove osdep.c/qemu-img code duplication
...
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11 21:35:42 +00:00
aurel32
1cdb9c3d82
Revert revisions r4168 and r4169. That's work in progress, not ready for trunk yet.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07 21:24:25 +00:00
aurel32
e755699dc7
Always enable precise emulation when softfloat is used
...
The patch below changes the way to enable softfloat on the PPC target. It
is now enabled when softfloat is used. The rationale behind this change
is that persons who want precise emulation prefer precision over emulation
speed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07 21:00:51 +00:00
aurel32
80621676af
Math functions helper for CONFIG_SOFTFLOAT=yes
...
The patch below adds isfinite() and isnormal() functions which can
work with float64 type, used when CONFIG_SOFTFLOAT=yes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4048 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13 19:20:00 +00:00
aurel32
0ca9d3807c
Use float32/64 instead of float/double
...
The patch below uses the float32 and float64 types instead of the float
and double types in the PPC code. This doesn't change anything when
using softfloat-native as the types are the same, but that helps
compiling the PPC target with softfloat.
It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and
use them instead of identical unions that are defined in numerous
places.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13 19:19:16 +00:00
aurel32
5567025f53
mtfsf: fix FPSCR_VX and FPSCR_FEX computation
...
The patch below fixes the computation of FPSCR_VX and FPSCR_FEX when
using the mtfsf instruction. As stated in the PowerPC manual the mtfsf
instruction can't alter those bit, and thus it should always be
computed.
Acked by Jocelyn Mayer.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4034 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-10 00:09:28 +00:00
bellard
57fec1fee9
use the TCG code generator
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01 10:50:11 +00:00
j_mayer
e9b34b3741
Cleanup: remove useless TARGET_GPR_BITS definition.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3799 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-10 08:13:09 +00:00
j_mayer
4e7774427d
Fix PowerPC 74xx definitions.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-10 07:40:16 +00:00
ths
01ba98161f
Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-09 02:22:57 +00:00
j_mayer
6b542af760
Fix incorrect debug prints (reported by Paul Brook).
...
Remove obsolete / duplicated debug prints and improve output consistency.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24 02:03:55 +00:00
j_mayer
69facb7897
Revert foolish patch.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23 22:16:59 +00:00
pbrook
9b605b9eae
Fix ppc32 register dumps on 64-bit hosts.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23 17:33:12 +00:00
j_mayer
e7c240035f
Add new sane low-level memory accessors for PowerPC that do proper
...
size or zero extension, with homogenous names.
Fix load & store strings: those are now endian-sensitive, by definition.
Fix dcbz: must always align the target address to a cache line boundary.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3719 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-22 11:00:46 +00:00
j_mayer
bd928ebafe
Fix PowerPC 7xx definitions.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-21 13:08:23 +00:00
j_mayer
082c6681b6
Remove shared macro used to define PowerPC implementations instructions sets:
...
tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 13:22:47 +00:00
j_mayer
add78955b0
PowerPC 620 MMU do not have the same exact behavior as standard
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64 bits PowerPC ones.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 11:41:10 +00:00
j_mayer
5b8105fa50
PowerPC instruction fixes:
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- hrfid is part of the hypervisor extension
- fix stfiwx naming
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3705 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 11:39:29 +00:00
j_mayer
c8623f2e37
Fix another collision in PowerPC instructions definitions.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3702 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 01:48:51 +00:00
j_mayer
4018bae916
New PowerPC CPU flag to define the decrementer and time-base source clock.
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Use it to properly initialize the clock for the PreP target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 01:48:12 +00:00
j_mayer
4c1b1bfe30
Improve PowerPC instructions set dump.
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Remove meaningless define from cpu.h
Misc cleanups.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 23:14:53 +00:00
j_mayer
80d11f4467
Add definitions for Freescale PowerPC implementations,
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ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
thus providing a way of testing their implementation specific instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 23:02:20 +00:00
j_mayer
b4095fed95
Define Freescale cores specific MMU model, exceptions and input bus.
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(but do not provide any actual implementation).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 22:42:36 +00:00
j_mayer
05332d70fd
A little more granularity in PowerPC instructions definition is needed
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in order to implement Freescale cores.
Fix efsadd / efssub opcodes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 22:26:51 +00:00
j_mayer
a4f30719a8
PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
...
Remove TARGET_PPC64 dependency and add code provision to be able
to define a fake 32 bits CPU with hypervisor feature support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 21:14:09 +00:00
j_mayer
f610349f36
Fix collision in PowerPC instructions definitions.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3668 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 12:01:45 +00:00
j_mayer
7820dbf3f0
Make the PowerPC MMU model, exception model and input bus model
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typedefed enums.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 02:16:14 +00:00
j_mayer
7b62a95504
Add missing definition for number of input pins for the PowerPC 970 bus.
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Use proper INPUT_NB definitions to allocate PowerPC input pins structure,
fixing a buffer overflow in the 6xx bus case.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 02:04:00 +00:00
j_mayer
b172c56a6d
Always make all PowerPC exception definitions visible.
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Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 01:37:44 +00:00
j_mayer
7863667f35
Always make PowerPC hypervisor mode memory accesses and instructions
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available for full system emulation, then removing all #if TARGET_PPC64H
from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
in target-ppc/translate.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3654 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-16 14:11:28 +00:00
j_mayer
57c26279c7
Fix PowerPC targets compilation on 32 bits hosts:
...
now that the SPE extension is available for all targets,
we always need to have some 64 bits temporary registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14 18:45:52 +00:00
j_mayer
271a916e8a
Fix invalid PowerPC 64 rldimi optimized case.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3638 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14 05:26:46 +00:00
j_mayer
1b413d5563
Reorganize PowerPC instructions categories, add icbi separate case.
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Fix frsqrtes instruction opcode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3636 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14 01:08:45 +00:00
j_mayer
c3e3682388
Add PVR and SPR definition for most embedded PowerPC from Freescale.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3632 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 23:40:49 +00:00
j_mayer
65d6c0f33c
PowerPC SPE extension fix: must always preserve GPR high bits when
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running in 32 bits mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 23:29:14 +00:00
j_mayer
3cd7d1ddbb
Allow use of SPE extension by all PowerPC targets,
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adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
and 36 bits physical address space.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 01:56:18 +00:00
j_mayer
a73666f656
More PowerPC target -1 usage fixes (reservation address).
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3627 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 00:50:50 +00:00
j_mayer
6f2d897872
Fix usage of the -1 constant in the PowerPC target code:
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fix invalid size casts and/or sign-extensions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3626 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12 00:04:48 +00:00
bellard
44f8625d23
fixed invalid type
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 12:35:55 +00:00
j_mayer
9c7e37e7fa
Fix POWER abs & abso computation.
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Fix PowerPC SPE evabs & evneg (thanks to Fabrice Bellard for reporting the bug)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3575 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 00:33:08 +00:00
j_mayer
c3e10c7b43
Optimize PowerPC overflow flag computation in most useful cases.
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Use the same routines to check overflow for addo, subfo and PowerPC 405
multiply and add cases.
Fix carry reset in addme(o) and subfme(o) cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3574 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 00:18:34 +00:00
j_mayer
ee4e83ed8d
Allow selection of PowerPC CPU giving a PVR.
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Remove unused pvr_mask field from CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 23:51:02 +00:00
bellard
aaed909a49
added cpu_model parameter to cpu_init()
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
j_mayer
056401eae6
PowerPC 601 need specific callbacks for its BATs setup.
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Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3524 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-04 02:55:33 +00:00
j_mayer
077fc2061e
Improve PowerPC CPU state dump.
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Dump NIP on SPR access faults.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3522 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-04 01:57:29 +00:00
j_mayer
2e13d23ac0
Fix PowerPC high BATs access: BAT number was incorrect.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3519 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03 14:23:07 +00:00
j_mayer
faadf50e29
PowerPC MMU and exception fixes:
...
* PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
later PowerPC implementation.
* Bugfix in BATs check: must not stop after 4 BATs when more are provided.
* Enable POWER 'rac' instruction.
* Fix exception prefix for all supported PowerPC implementations.
* Fix exceptions, MMU model and bus model for PowerPC 601 & 620.
* Enable PowerPC 620 as it could mostly boot a PreP target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3518 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03 13:37:12 +00:00
j_mayer
9fceefa7d1
Don't print any message when a priviledge exception occurs on mfpvr
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as the Linux allows applications to read this register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3510 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-02 22:47:50 +00:00
j_mayer
5b52b9911f
Fix PowerPC program exception that was broken by FPU exception patches
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(bug reported by Jason Wessel)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3509 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-02 22:35:33 +00:00
j_mayer
fc0d441e14
Fix CR ops with complement, thanks to Julian Seward for testing
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and reporting the bug :
* remove bugged CR ops specific micro-ops
* use standard and / or / shift operations instead
* comment not-used-anymore op_store_T1_crf_crf micro-op template.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3501 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-31 22:02:17 +00:00
j_mayer
86c4a9f513
Fix two PowerPC FPU emulation bugs (thanks to Aurelien Jarno)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3487 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 21:54:35 +00:00
ths
273af66025
Adjust s390 addresses (the MSB is defined as "to be ignored").
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 14:39:49 +00:00
j_mayer
603fcccece
Make Alpha and PowerPC targets use shared helpers
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for clz, clo, ctz, cto and ctpop.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3466 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28 12:54:53 +00:00
j_mayer
a11b8151df
PowerPC coding style and inlining fixes.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28 00:55:05 +00:00
j_mayer
5bda28432f
PowerPC floating-point helper typo.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3460 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 23:34:30 +00:00
j_mayer
4f8eb6cfa2
PowerPC float bugfix: 64 bits float mantissa is 52 bits long.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3459 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 17:59:46 +00:00
j_mayer
7c58044c0a
Fix PowerPC FPSCR update and floating-point exception generation
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in most useful cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 17:54:30 +00:00
j_mayer
8378e71f13
Fix endianness bug for PowerPC stfiwx instruction.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3456 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 17:18:49 +00:00
j_mayer
f0685f6e7a
For consistency, align the address to the cache line before using it,
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when invalidating the instruction cache.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3449 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 00:55:17 +00:00
j_mayer
dac454af57
Bugfix in PowerPC dcbi instruction:
...
we must do a load before the store, or we'll store random data.
Update cache instructions comments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3448 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 00:48:00 +00:00
j_mayer
c7697e1f51
Pretty dump for specific PowerPC instructions names.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3447 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 00:46:07 +00:00
j_mayer
f9fdea6b85
Make PowerPC hypervisor resources able to compile, even if not enabled for now.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3446 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 00:38:37 +00:00
j_mayer
2c1ee068b4
Bugfix: PowerPC 64 slbia never invalidates the first segment entry.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3445 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 00:37:04 +00:00
j_mayer
88ad920b8a
Fix PowerPC 64x64 bits multiplication overflow check.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3444 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 23:36:08 +00:00
j_mayer
9d901a201b
Use host-utils for PowerPC 64 64x64 bits multiplications.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3442 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 23:28:36 +00:00
j_mayer
cd346349b4
Add PowerPC power-management state check callback.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3441 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 23:27:04 +00:00
j_mayer
2f462816ac
Implement power-management for all defined PowerPC CPUs.
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Fix PowerPC 970MP definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3440 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 23:14:50 +00:00
j_mayer
86f1d3ac73
Update PowerPC emulation status file.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3438 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 21:38:16 +00:00
j_mayer
8ca3f6c382
Allow selection of all defined PowerPC 74xx (aka G4) CPUs.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3437 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 21:37:25 +00:00
j_mayer
0411a97258
Gprof prooved the PowerPC emulation spent too much time in MSR load and store
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routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code.
Allow entering halt mode as the result of a rfi instruction.
Add a new helper_regs.h file to avoid duplication of special registers
manipulation routines (currently XER and MSR).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3436 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25 21:35:50 +00:00
j_mayer
b227a8e9aa
Properly implement non-execute bit on PowerPC segments and PTEs.
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Fix page protection bits for PowerPC 64 MMU.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 10:21:20 +00:00
j_mayer
d68f13063b
Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.
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Avoid hardcoding PowerPC interrupts definitions to ease updates.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3393 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 09:27:16 +00:00
j_mayer
a13d7523cb
There is no need of a specific MMU model for PowerPC 601.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 09:14:08 +00:00
j_mayer
eacc324914
Implement PowerPC 64 SLB invalidation helpers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3391 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 09:06:19 +00:00
j_mayer
e63ecc6f68
Do not allow PowerPC CPU restart after entering checkstop mode.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3388 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 08:48:23 +00:00
j_mayer
1e42b8f06d
Generate micro-ops for PowerPC hypervisor mode.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3386 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 08:27:14 +00:00
j_mayer
6ebbf39000
Replace is_user variable with mmu_idx in softmmu core,
...
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 07:07:08 +00:00
j_mayer
c732abe222
Unify '-cpu ?' option.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-12 06:47:46 +00:00
j_mayer
9b22787cda
Update PowerPC emulation status file.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3355 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 03:00:35 +00:00
j_mayer
25ba3a6812
Remove synonymous in PowerPC MSR bits definitions.
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Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3354 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 02:58:07 +00:00
j_mayer
141c8ae225
Real-mode only PowerPC 40x do not have any TLBs.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3353 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 02:44:11 +00:00
j_mayer
4e80effcf9
Implement exception prefix feature for PowerPC 601.
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Fix PowerPC 601 hardware reset vector.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3352 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 02:35:41 +00:00
j_mayer
7a3a6927b6
Add missing exception vectors for PowerPC 7x5.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3351 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08 02:23:00 +00:00
j_mayer
417bf01068
Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3350 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 23:10:08 +00:00
j_mayer
a9d9eb8fd4
Implement PowerPC Altivec load & stores, used by Apple firmware for memcpy.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 18:19:26 +00:00
j_mayer
b33c17e12d
PowerPC target coding style fixes.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 17:30:34 +00:00
j_mayer
b068d6a713
PowerPC target optimisations: make intensive use of always_inline.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3347 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 17:13:44 +00:00
j_mayer
f2e63a42c9
Reorganize the CPUPPCState structure to group features.
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Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07 15:43:50 +00:00