Aleksandar Markovic 04992c8cd1 target/mips: Amend preprocessor constants for CP0 registers ... Correct existing CP0-related preprocessor constants (replace "CPO" with "CP0" (form letter "O" to digit "0", when needed). Besides, add preprocessor constants for CP0 subregisters. The names of the subregisters were chosen to be in sync with the table of corresponding assembler mnemonics found in the documentation for I6500 and I6400 (release 1.0). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>		2019-01-18 16:53:28 +01:00
..
cp0_timer.c
cpu-qom.h
cpu.c	target/mips: Add disassembler support for nanoMIPS	2018-10-25 22:13:33 +02:00
cpu.h	target/mips: Amend preprocessor constants for CP0 registers	2019-01-18 16:53:28 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: Implement hardware page table walker for MIPS32	2018-10-18 20:37:20 +02:00
helper.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
kvm.c
kvm_mips.h
lmi_helper.c
machine.c	target/mips: Add fields for SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-10-29 14:13:47 +01:00
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Update ITU to utilize SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
TODO
trace-events
translate.c	target/mips: Amend preprocessor constants for CP0 registers	2019-01-18 16:53:28 +01:00
translate_init.inc.c	target/mips: Disable R5900 support	2018-11-17 19:29:34 +01:00