Apple uses an IBM MPIC2A without timers, it has 64 sources. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
537 lines
19 KiB
C
537 lines
19 KiB
C
/*
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* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* PCI bus layout on a real G5 (U3 based):
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*
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* 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
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* 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
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* 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
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* 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
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* 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
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* 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
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* 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
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* 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
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* 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
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* 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
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* 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
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* 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
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* 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
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* 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/mac.h"
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#include "hw/input/adb.h"
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#include "hw/ppc/mac_dbdma.h"
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#include "hw/timer/m48t59.h"
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#include "hw/pci/pci.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/char/escc.h"
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#include "hw/ppc/openpic.h"
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#include "hw/ide.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "hw/usb.h"
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#include "sysemu/block-backend.h"
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#include "exec/address-spaces.h"
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#include "hw/sysbus.h"
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#include "qemu/cutils.h"
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#include "trace.h"
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#define MAX_IDE_BUS 2
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#define CFG_ADDR 0xf0000510
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#define TBFREQ (100UL * 1000UL * 1000UL)
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#define CLOCKFREQ (900UL * 1000UL * 1000UL)
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#define BUSFREQ (100UL * 1000UL * 1000UL)
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#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
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/* UniN device */
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static void unin_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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trace_mac99_uninorth_write(addr, value);
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if (addr == 0x0) {
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*(int*)opaque = value;
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}
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}
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static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
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{
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uint32_t value;
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value = 0;
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switch (addr) {
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case 0:
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value = *(int*)opaque;
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}
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trace_mac99_uninorth_read(addr, value);
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return value;
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}
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static const MemoryRegionOps unin_ops = {
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.read = unin_read,
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.write = unin_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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static void ppc_core99_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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/* 970 CPUs want to get their initial IP as part of their boot protocol */
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cpu->env.nip = PROM_ADDR + 0x100;
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}
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/* PowerPC Mac99 hardware initialisation */
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static void ppc_core99_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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const char *boot_device = machine->boot_order;
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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char *filename;
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qemu_irq *pic, **openpic_irqs;
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MemoryRegion *isa = g_new(MemoryRegion, 1);
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MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
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MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
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int linux_boot, i, j, k;
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MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
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hwaddr kernel_base, initrd_base, cmdline_base = 0;
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long kernel_size, initrd_size;
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PCIBus *pci_bus;
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PCIDevice *macio;
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MACIOIDEState *macio_ide;
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BusState *adb_bus;
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MacIONVRAMState *nvr;
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int bios_size, ndrv_size;
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uint8_t *ndrv_file;
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MemoryRegion *pic_mem, *escc_mem;
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MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
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int ppc_boot_device;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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void *fw_cfg;
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int machine_arch;
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SysBusDevice *s;
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DeviceState *dev;
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int *token = g_new(int, 1);
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hwaddr nvram_addr = 0xFFF04000;
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uint64_t tbfreq;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (machine->cpu_model == NULL) {
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#ifdef TARGET_PPC64
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machine->cpu_model = "970fx";
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#else
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machine->cpu_model = "G4";
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#endif
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}
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for (i = 0; i < smp_cpus; i++) {
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cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
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machine->cpu_model));
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env = &cpu->env;
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, TBFREQ);
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qemu_register_reset(ppc_core99_reset, cpu);
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}
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/* allocate RAM */
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memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
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memory_region_add_subregion(get_system_memory(), 0, ram);
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/* allocate and load BIOS */
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memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
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&error_fatal);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
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/* Load OpenBIOS (ELF) */
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if (filename) {
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bios_size = load_elf(filename, NULL, NULL, NULL,
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NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
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g_free(filename);
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} else {
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bios_size = -1;
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}
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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error_report("could not load PowerPC bios '%s'", bios_name);
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exit(1);
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}
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if (linux_boot) {
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uint64_t lowaddr = 0;
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_base = KERNEL_LOAD_ADDR;
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
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0, 0);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, kernel_base,
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ram_size - kernel_base, bswap_needed,
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TARGET_PAGE_SIZE);
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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kernel_base,
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ram_size - kernel_base);
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if (kernel_size < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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exit(1);
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}
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cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
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} else {
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initrd_base = 0;
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initrd_size = 0;
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cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
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}
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ppc_boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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ppc_boot_device = '\0';
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/* We consider that NewWorld PowerMac never have any floppy drive
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* For now, OHW cannot boot from the network.
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*/
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for (i = 0; boot_device[i] != '\0'; i++) {
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if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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break;
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}
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}
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if (ppc_boot_device == '\0') {
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fprintf(stderr, "No valid boot device for Mac99 machine\n");
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exit(1);
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}
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}
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/* Register 8 MB of ISA IO space */
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memory_region_init_alias(isa, NULL, "isa_mmio",
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get_system_io(), 0, 0x00800000);
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memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
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/* UniN init: XXX should be a real device */
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memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
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memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
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memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
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memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
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openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
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openpic_irqs[0] =
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g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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for (i = 0; i < smp_cpus; i++) {
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/* Mac99 IRQ connection between OpenPIC outputs pins
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* and PowerPC input pins
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*/
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
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break;
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_INPUT_970:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
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break;
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#endif /* defined(TARGET_PPC64) */
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default:
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error_report("Bus model not supported on mac99 machine");
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exit(1);
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}
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}
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pic = g_new0(qemu_irq, 64);
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dev = qdev_create(NULL, TYPE_OPENPIC);
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qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_KEYLARGO);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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pic_mem = s->mmio[0].memory;
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k = 0;
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for (i = 0; i < smp_cpus; i++) {
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for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
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}
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}
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for (i = 0; i < 64; i++) {
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pic[i] = qdev_get_gpio_in(dev, i);
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}
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if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
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/* 970 gets a U3 bus */
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pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
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machine_arch = ARCH_MAC99_U3;
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} else {
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pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
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machine_arch = ARCH_MAC99;
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}
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object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort);
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machine->usb |= defaults_enabled() && !machine->usb_disabled;
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/* Timebase Frequency */
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if (kvm_enabled()) {
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tbfreq = kvmppc_get_tbfreq();
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} else {
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tbfreq = TBFREQ;
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}
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/* init basic PC hardware */
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escc_mem = escc_init(0, pic[0x25], pic[0x24],
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serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
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memory_region_init_alias(escc_bar, NULL, "escc-bar",
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escc_mem, 0, memory_region_size(escc_mem));
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macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
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dev = DEVICE(macio);
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qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
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qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
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qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
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qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
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qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
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qdev_prop_set_uint64(dev, "frequency", tbfreq);
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macio_init(macio, pic_mem, escc_bar);
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/* We only emulate 2 out of 3 IDE controllers for now */
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ide_drive_get(hd, ARRAY_SIZE(hd));
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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"ide[0]"));
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macio_ide_init_drives(macio_ide, hd);
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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"ide[1]"));
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macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
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dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
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adb_bus = qdev_get_child_bus(dev, "adb.0");
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dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
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qdev_init_nofail(dev);
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dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
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qdev_init_nofail(dev);
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if (machine->usb) {
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pci_create_simple(pci_bus, -1, "pci-ohci");
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/* U3 needs to use USB for input because Linux doesn't support via-cuda
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on PPC64 */
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if (machine_arch == ARCH_MAC99_U3) {
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|
USBBus *usb_bus = usb_bus_find(-1);
|
|
|
|
usb_create_simple(usb_bus, "usb-kbd");
|
|
usb_create_simple(usb_bus, "usb-mouse");
|
|
}
|
|
}
|
|
|
|
pci_vga_init(pci_bus);
|
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
|
|
graphic_depth = 15;
|
|
}
|
|
|
|
for (i = 0; i < nb_nics; i++) {
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
|
|
}
|
|
|
|
/* The NewWorld NVRAM is not located in the MacIO device */
|
|
#ifdef CONFIG_KVM
|
|
if (kvm_enabled() && getpagesize() > 4096) {
|
|
/* We can't combine read-write and read-only in a single page, so
|
|
move the NVRAM out of ROM again for KVM */
|
|
nvram_addr = 0xFFE00000;
|
|
}
|
|
#endif
|
|
dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
|
|
qdev_prop_set_uint32(dev, "size", 0x2000);
|
|
qdev_prop_set_uint32(dev, "it_shift", 1);
|
|
qdev_init_nofail(dev);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
|
|
nvr = MACIO_NVRAM(dev);
|
|
pmac_format_nvram_partition(nvr, 0x2000);
|
|
/* No PCI init: the BIOS will do it */
|
|
|
|
fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
if (kernel_cmdline) {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
|
|
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
|
|
} else {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
|
}
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
|
if (kvm_enabled()) {
|
|
#ifdef CONFIG_KVM
|
|
uint8_t *hypercall;
|
|
|
|
hypercall = g_malloc(16);
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
|
#endif
|
|
}
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
|
|
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
|
|
|
|
/* MacOS NDRV VGA driver */
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
|
|
if (filename) {
|
|
ndrv_size = get_image_size(filename);
|
|
if (ndrv_size != -1) {
|
|
ndrv_file = g_malloc(ndrv_size);
|
|
ndrv_size = load_image(filename, ndrv_file);
|
|
|
|
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
|
|
}
|
|
g_free(filename);
|
|
}
|
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
|
}
|
|
|
|
static int core99_kvm_type(const char *arg)
|
|
{
|
|
/* Always force PR KVM */
|
|
return 2;
|
|
}
|
|
|
|
static void core99_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Mac99 based PowerMAC";
|
|
mc->init = ppc_core99_init;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->max_cpus = MAX_CPUS;
|
|
mc->default_boot_order = "cd";
|
|
mc->kvm_type = core99_kvm_type;
|
|
}
|
|
|
|
static const TypeInfo core99_machine_info = {
|
|
.name = MACHINE_TYPE_NAME("mac99"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = core99_machine_class_init,
|
|
};
|
|
|
|
static void mac_machine_register_types(void)
|
|
{
|
|
type_register_static(&core99_machine_info);
|
|
}
|
|
|
|
type_init(mac_machine_register_types)
|