ad40be2708
Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. Add kvm_riscv.h to place riscv specific interface. In addition, PLIC is created without M-mode PLIC contexts when KVM is enabled. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-id: 20220112081329.1835-7-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35 lines
811 B
Meson
35 lines
811 B
Meson
# FIXME extra_args should accept files()
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dir = meson.current_source_dir()
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gen = [
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decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
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decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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]
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riscv_ss = ss.source_set()
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riscv_ss.add(gen)
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riscv_ss.add(files(
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'cpu.c',
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'cpu_helper.c',
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'csr.c',
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'fpu_helper.c',
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'gdbstub.c',
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'op_helper.c',
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'vector_helper.c',
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'bitmanip_helper.c',
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'translate.c',
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'm128_helper.c'
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))
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riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
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riscv_softmmu_ss = ss.source_set()
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riscv_softmmu_ss.add(files(
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'arch_dump.c',
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'pmp.c',
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'monitor.c',
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'machine.c'
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))
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target_arch += {'riscv': riscv_ss}
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target_softmmu_arch += {'riscv': riscv_softmmu_ss}
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