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Peter Maydell ef475b5dd1 target-arm: 
* cleanups converting to DEFINE_PROP_LINK
  * allwinner-a10: mark as not user-creatable
  * initial patches working towards ARMv8M support
  * implement generating aborts on memory transaction failures
  * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907' into staging

target-arm:
 * cleanups converting to DEFINE_PROP_LINK
 * allwinner-a10: mark as not user-creatable
 * initial patches working towards ARMv8M support
 * implement generating aborts on memory transaction failures
 * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later

# gpg: Signature made Thu 07 Sep 2017 14:26:07 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits)
  target/arm: Add Jazelle feature
  target/arm: Implement new do_transaction_failed hook
  hw/arm: Set ignore_memory_transaction_failures for most ARM boards
  boards.h: Define new flag ignore_memory_transaction_failures
  target/arm: Implement BXNS, and banked stack pointers
  target/arm: Move regime_is_secure() to target/arm/internals.h
  target/arm: Make CFSR register banked for v8M
  target/arm: Make MMFAR banked for v8M
  target/arm: Make CCR register banked for v8M
  target/arm: Make MPU_CTRL register banked for v8M
  target/arm: Make MPU_RNR register banked for v8M
  target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
  target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
  target/arm: Make VTOR register banked for v8M
  nvic: Add NS alias SCS region
  target/arm: Make CONTROL register banked for v8M
  target/arm: Make FAULTMASK register banked for v8M
  target/arm: Make PRIMASK register banked for v8M
  target/arm: Make BASEPRI register banked for v8M
  target/arm: Add MMU indexes for secure v8M
  ...

# Conflicts:
#	target/arm/translate.c
2017-09-07 16:46:15 +01:00
..
alpha alpha: replace cpu_alpha_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
arm target-arm: 2017-09-07 16:46:15 +01:00
cris target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
hppa hppa: replace cpu_hppa_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
i386 target/i386: [tcg] Port to generic translation framework 2017-09-06 08:06:47 -07:00
lm32 target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
m68k target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
microblaze target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
mips target/mips: Fix RDHWR CC with icount 2017-08-02 22:18:13 +01:00
moxie moxie: replace cpu_moxie_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
nios2 target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
openrisc target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
ppc ppc: replace cpu_ppc_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
s390x target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
sh4 sh4: replace cpu_sh4_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
sparc sparc: replace cpu_sparc_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
tilegx tilegx: replace cpu_tilegx_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
tricore tricore: replace cpu_tricore_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
unicore32 target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
xtensa target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00