3bf03f0899
We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* SiFive CLINT (Core Local Interruptor) interface
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_CLINT_H
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#define HW_SIFIVE_CLINT_H
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#include "hw/sysbus.h"
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#define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
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#define SIFIVE_CLINT(obj) \
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OBJECT_CHECK(SiFiveCLINTState, (obj), TYPE_SIFIVE_CLINT)
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typedef struct SiFiveCLINTState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t hartid_base;
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uint32_t num_harts;
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uint32_t sip_base;
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uint32_t timecmp_base;
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uint32_t time_base;
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uint32_t aperture_size;
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} SiFiveCLINTState;
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DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
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uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
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uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
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enum {
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SIFIVE_SIP_BASE = 0x0,
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SIFIVE_TIMECMP_BASE = 0x4000,
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SIFIVE_TIME_BASE = 0xBFF8
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};
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enum {
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SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
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};
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#endif
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