The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
295 lines
8.8 KiB
C
295 lines
8.8 KiB
C
/*
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* Nuvoton NPCM7xx Clock Control Registers.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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#include "sysemu/watchdog.h"
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#define PLLCON_LOKI BIT(31)
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#define PLLCON_LOKS BIT(30)
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#define PLLCON_PWDEN BIT(12)
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enum NPCM7xxCLKRegisters {
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NPCM7XX_CLK_CLKEN1,
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NPCM7XX_CLK_CLKSEL,
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NPCM7XX_CLK_CLKDIV1,
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NPCM7XX_CLK_PLLCON0,
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NPCM7XX_CLK_PLLCON1,
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NPCM7XX_CLK_SWRSTR,
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NPCM7XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
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NPCM7XX_CLK_IPSRST2,
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NPCM7XX_CLK_CLKEN2,
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NPCM7XX_CLK_CLKDIV2,
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NPCM7XX_CLK_CLKEN3,
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NPCM7XX_CLK_IPSRST3,
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NPCM7XX_CLK_WD0RCR,
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NPCM7XX_CLK_WD1RCR,
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NPCM7XX_CLK_WD2RCR,
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NPCM7XX_CLK_SWRSTC1,
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NPCM7XX_CLK_SWRSTC2,
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NPCM7XX_CLK_SWRSTC3,
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NPCM7XX_CLK_SWRSTC4,
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NPCM7XX_CLK_PLLCON2,
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NPCM7XX_CLK_CLKDIV3,
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NPCM7XX_CLK_CORSTC,
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NPCM7XX_CLK_PLLCONG,
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NPCM7XX_CLK_AHBCKFI,
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NPCM7XX_CLK_SECCNT,
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NPCM7XX_CLK_CNTR25M,
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NPCM7XX_CLK_REGS_END,
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};
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/*
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* These reset values were taken from version 0.91 of the NPCM750R data sheet.
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*
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* All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
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* core domain reset, but this reset type is not yet supported by QEMU.
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*/
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static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
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[NPCM7XX_CLK_CLKEN1] = 0xffffffff,
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[NPCM7XX_CLK_CLKSEL] = 0x004aaaaa,
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[NPCM7XX_CLK_CLKDIV1] = 0x5413f855,
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[NPCM7XX_CLK_PLLCON0] = 0x00222101 | PLLCON_LOKI,
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[NPCM7XX_CLK_PLLCON1] = 0x00202101 | PLLCON_LOKI,
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[NPCM7XX_CLK_IPSRST1] = 0x00001000,
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[NPCM7XX_CLK_IPSRST2] = 0x80000000,
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[NPCM7XX_CLK_CLKEN2] = 0xffffffff,
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[NPCM7XX_CLK_CLKDIV2] = 0xaa4f8f9f,
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[NPCM7XX_CLK_CLKEN3] = 0xffffffff,
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[NPCM7XX_CLK_IPSRST3] = 0x03000000,
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[NPCM7XX_CLK_WD0RCR] = 0xffffffff,
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[NPCM7XX_CLK_WD1RCR] = 0xffffffff,
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[NPCM7XX_CLK_WD2RCR] = 0xffffffff,
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[NPCM7XX_CLK_SWRSTC1] = 0x00000003,
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[NPCM7XX_CLK_PLLCON2] = 0x00c02105 | PLLCON_LOKI,
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[NPCM7XX_CLK_CORSTC] = 0x04000003,
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[NPCM7XX_CLK_PLLCONG] = 0x01228606 | PLLCON_LOKI,
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[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
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};
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/* Register Field Definitions */
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#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
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/* The number of watchdogs that can trigger a reset. */
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#define NPCM7XX_NR_WATCHDOGS (3)
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static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxCLKState *s = opaque;
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int64_t now_ns;
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uint32_t value = 0;
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if (reg >= NPCM7XX_CLK_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
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__func__, offset);
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return 0;
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}
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switch (reg) {
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case NPCM7XX_CLK_SWRSTR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
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__func__, offset);
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break;
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case NPCM7XX_CLK_SECCNT:
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now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND;
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break;
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case NPCM7XX_CLK_CNTR25M:
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now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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/*
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* This register counts 25 MHz cycles, updating every 640 ns. It rolls
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* over to zero every second.
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*
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* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
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*/
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value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
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break;
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default:
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value = s->regs[reg];
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break;
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};
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trace_npcm7xx_clk_read(offset, value);
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return value;
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}
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static void npcm7xx_clk_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxCLKState *s = opaque;
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uint32_t value = v;
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trace_npcm7xx_clk_write(offset, value);
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if (reg >= NPCM7XX_CLK_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
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__func__, offset);
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return;
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}
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switch (reg) {
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case NPCM7XX_CLK_SWRSTR:
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qemu_log_mask(LOG_UNIMP, "%s: SW reset not implemented: 0x%02x\n",
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__func__, value);
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value = 0;
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break;
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case NPCM7XX_CLK_PLLCON0:
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case NPCM7XX_CLK_PLLCON1:
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case NPCM7XX_CLK_PLLCON2:
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case NPCM7XX_CLK_PLLCONG:
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if (value & PLLCON_PWDEN) {
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/* Power down -- clear lock and indicate loss of lock */
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value &= ~PLLCON_LOKI;
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value |= PLLCON_LOKS;
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} else {
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/* Normal mode -- assume always locked */
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value |= PLLCON_LOKI;
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/* Keep LOKS unchanged unless cleared by writing 1 */
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if (value & PLLCON_LOKS) {
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value &= ~PLLCON_LOKS;
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} else {
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value |= (value & PLLCON_LOKS);
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}
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}
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break;
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case NPCM7XX_CLK_CNTR25M:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
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__func__, offset);
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return;
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}
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s->regs[reg] = value;
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}
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/* Perform reset action triggered by a watchdog */
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static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
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int level)
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{
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NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
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uint32_t rcr;
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g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
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rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];
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if (rcr & NPCM7XX_CLK_WDRCR_CA9C) {
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watchdog_perform_action();
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} else {
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qemu_log_mask(LOG_UNIMP,
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"%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
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__func__, rcr);
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}
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}
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static const struct MemoryRegionOps npcm7xx_clk_ops = {
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.read = npcm7xx_clk_read,
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.write = npcm7xx_clk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
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QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
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switch (type) {
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case RESET_TYPE_COLD:
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memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
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s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return;
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}
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/*
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* A small number of registers need to be reset on a core domain reset,
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* but no such reset type exists yet.
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*/
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qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.",
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__func__, type);
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}
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static void npcm7xx_clk_init(Object *obj)
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{
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NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
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memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
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TYPE_NPCM7XX_CLK, 4 * KiB);
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sysbus_init_mmio(&s->parent, &s->iomem);
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qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
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NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
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}
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static const VMStateDescription vmstate_npcm7xx_clk = {
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.name = "npcm7xx-clk",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
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VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
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dc->desc = "NPCM7xx Clock Control Registers";
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dc->vmsd = &vmstate_npcm7xx_clk;
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rc->phases.enter = npcm7xx_clk_enter_reset;
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}
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static const TypeInfo npcm7xx_clk_info = {
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.name = TYPE_NPCM7XX_CLK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxCLKState),
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.instance_init = npcm7xx_clk_init,
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.class_init = npcm7xx_clk_class_init,
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};
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static void npcm7xx_clk_register_type(void)
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{
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type_register_static(&npcm7xx_clk_info);
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}
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type_init(npcm7xx_clk_register_type);
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