Lara Lazier 7eb54ca95d target/i386: Added consistency checks for VMRUN intercept and ASID ... Zero VMRUN intercept and ASID should cause an immediate VMEXIT during the consistency checks performed by VMRUN. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-3-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2021-06-16 15:02:40 +02:00
..
sysemu	target/i386: Added consistency checks for VMRUN intercept and ASID	2021-06-16 15:02:40 +02:00
user	target/i386: Remove user-only i/o stubs	2021-05-19 12:17:23 -05:00
bpt_helper.c	target/i386: Mark some helpers as noreturn	2021-05-19 12:17:11 -05:00
cc_helper.c	i386: move TCG cpu class initialization to tcg/	2020-12-16 15:50:33 -05:00
cc_helper_template.h
excp_helper.c	target/i386: Mark some helpers as noreturn	2021-05-19 12:17:11 -05:00
fpu_helper.c	softfloat: Introduce Floatx80RoundPrec	2021-06-03 14:04:02 -07:00
helper-tcg.h	target/i386: Move invlpg, hlt, monitor, mwait to sysemu	2021-05-19 12:17:11 -05:00
int_helper.c	i386: move TCG cpu class initialization to tcg/	2020-12-16 15:50:33 -05:00
mem_helper.c	exec: Use cpu_untagged_addr in g2h; split out g2h_untagged	2021-02-16 11:04:53 +00:00
meson.build	i386: split svm_helper into sysemu and stub-only user	2021-05-10 15:41:51 -04:00
misc_helper.c	target/i386: Move invlpg, hlt, monitor, mwait to sysemu	2021-05-19 12:17:11 -05:00
mpx_helper.c	i386: move TCG cpu class initialization to tcg/	2020-12-16 15:50:33 -05:00
seg_helper.c	target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa	2021-06-04 13:47:08 +02:00
seg_helper.h	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
tcg-cpu.c	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
tcg-cpu.h	i386: split off sysemu-only functionality in tcg-cpu	2021-05-10 15:41:50 -04:00
tcg-stub.c
translate.c	target/i386: Fix decode of cr8	2021-06-04 13:47:08 +02:00