Michael Clark f18637cd61 RISC-V: Add misa runtime write support ... This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-02-11 15:56:22 -08:00
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cpu.c	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu_bits.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
csr.c	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Add misa.MAFD checks to translate	2019-02-11 15:56:22 -08:00