Hesham Almatary f8162068f1 RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off ... The current implementation returns 1 (PMP check success) if the address is in range even if the PMP entry is off. This is a bug. For example, if there is a PMP check in S-Mode which is in range, but its PMP entry is off, this will succeed, which it should not. The patch fixes this bug by only checking the PMP permissions if the address is in range and its corresponding PMP entry it not off. Otherwise, it will keep the ret = -1 which will be checked and handled correctly at the end of the function. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-06-23 23:44:42 -07:00
..
insn_trans	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: Implement riscv_cpu_unassigned_access	2019-06-23 23:44:41 -07:00
cpu.h	RISC-V: Check PMP during Page Table Walks	2019-06-23 23:44:42 -07:00
cpu_bits.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu_helper.c	RISC-V: Check PMP during Page Table Walks	2019-06-23 23:44:42 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-24 12:09:22 -07:00
instmap.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
op_helper.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-06-23 23:44:42 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events	RISC-V: Convert trap debugging to trace events	2019-03-19 05:14:40 -07:00
translate.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00