59 lines
2.0 KiB
Makefile
59 lines
2.0 KiB
Makefile
#******************************************************************************
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# * *** ***
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# *** *** ***
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# *** **** ********** *** ***** *** **** *****
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# ********* ********** *** ********* ************ *********
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# **** *** *** *** *** **** ***
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# *** *** ****** *** *********** *** **** *****
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# *** *** ****** *** ************* *** **** *****
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# *** **** **** *** *** *** **** ***
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# *** ******* ***** ************** ************* *********
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# *** ***** *** ******* ** ** ****** *****
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# t h e r e a l t i m e t a r g e t e x p e r t s
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#
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# http://www.rt-labs.com
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# Copyright (C) 2006. rt-labs AB, Sweden. All rights reserved.
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#------------------------------------------------------------------------------
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# $Id: app.mk 452 2013-02-26 21:02:58Z smf.arthur $
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#------------------------------------------------------------------------------
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OBJDIR = obj/$(ARCH)
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LIBS += oshw osal soem
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include $(PRJ_ROOT)/make/rules.mk
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include $(PRJ_ROOT)/make/files.mk
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ifeq ($(ARCH),linux)
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LIBS += -lpthread -lrt
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endif
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SUBDIRS = $(patsubst %/,%,$(dir $(wildcard */Makefile)))
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# Use .PHONY so link step always occurs. This is a simple way
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# to avoid computing dependencies on libs
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.PHONY: $(APPNAME)
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$(APPNAME): $(OBJDIR) $(SUBDIRS) $(OBJDIR_OBJS) $(EXTRA_OBJS)
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@echo --- Linking $@
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$(SILENT)$(CC) $(LDFLAGS) $(LD_PATHS) $(OBJDIR)/*.o -o $@ $(LIBS)
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$(OBJDIR):
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@test -e $(OBJDIR) || $(MKDIR) $(OBJDIR)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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@echo --- Entering $(CURDIR)/$@
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@$(MAKE) -C $@ $(MAKECMDGOALS)
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@echo --- Leaving $(CURDIR)/$@
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.PHONY: clean
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clean: $(SUBDIRS)
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@$(RM) $(OBJDIR)/*
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rm -rf obj/
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@$(RM) $(APPNAME)
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@$(RM) $(APPNAME).elf
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@$(RM) $(APPNAME).map
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ifneq ($(MAKECMDGOALS),clean)
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-include $(DEPENDS)
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endif
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