Enable SM3 interrupt for input only slave
Enable SM3 interrupt if the slave only got inputs. On PREOP_TO_SAFEOP do an intial write to SM3, otherwise the SM3 will never occur since there is no data present to read.pull/120/head
parent
48c80f5cae
commit
8ebb78ea10
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@ -38,6 +38,13 @@ void cb_state_change (uint8_t * as, uint8_t * an)
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/* Enable watchdog interrupt */
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/* Enable watchdog interrupt */
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ESC_ALeventmaskwrite (ESC_ALeventmaskread() | ESCREG_ALEVENT_WD);
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ESC_ALeventmaskwrite (ESC_ALeventmaskread() | ESCREG_ALEVENT_WD);
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}
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}
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else if (*as == PREOP_TO_SAFEOP)
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{
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/* Write initial input data requried if an input only slave,
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* otherwise the SM3 will never occur.
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*/
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DIG_process (DIG_PROCESS_INPUTS_FLAG);
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}
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}
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}
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/* Setup of DC */
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/* Setup of DC */
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@ -70,6 +77,7 @@ int main (void)
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.esc_hw_interrupt_disable = ESC_interrupt_disable,
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.esc_hw_interrupt_disable = ESC_interrupt_disable,
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.esc_hw_eep_handler = ESC_eep_handler,
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.esc_hw_eep_handler = ESC_eep_handler,
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.esc_check_dc_handler = dc_checker
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.esc_check_dc_handler = dc_checker
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.get_device_id = NULL
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};
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};
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rprintf ("Hello world\n");
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rprintf ("Hello world\n");
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26
soes/esc.c
26
soes/esc.c
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@ -707,7 +707,7 @@ uint8_t ESC_checkSM23 (uint8_t state)
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}
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}
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/* SM disabled and (SM activated or length > 0) set by master */
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/* SM disabled and (SM activated or length > 0) set by master */
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else if (((ESC_SM2_act & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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else if (((ESC_SM2_act & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) || (etohs (SM->Length) > 0)))
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) || (ESCvar.ESC_SM2_sml > 0)))
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{
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{
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ESCvar.SMtestresult = SMRESULT_ERRSM2;
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ESCvar.SMtestresult = SMRESULT_ERRSM2;
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/* fail state change */
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/* fail state change */
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@ -716,7 +716,7 @@ uint8_t ESC_checkSM23 (uint8_t state)
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/* SM enabled and (length > 0 but SM disabled) set by master */
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/* SM enabled and (length > 0 but SM disabled) set by master */
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else if (((ESC_SM2_act & ESCREG_SYNC_ACT_ACTIVATED) > 0) &&
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else if (((ESC_SM2_act & ESCREG_SYNC_ACT_ACTIVATED) > 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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(etohs (SM->Length) > 0))
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(ESCvar.ESC_SM2_sml > 0))
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{
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{
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ESCvar.SMtestresult = SMRESULT_ERRSM2;
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ESCvar.SMtestresult = SMRESULT_ERRSM2;
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/* fail state change */
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/* fail state change */
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@ -750,7 +750,7 @@ uint8_t ESC_checkSM23 (uint8_t state)
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}
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}
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/* SM disabled and (SM activated or length > 0) set by master */
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/* SM disabled and (SM activated or length > 0) set by master */
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else if (((ESC_SM3_act & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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else if (((ESC_SM3_act & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) || (etohs (SM->Length) > 0)))
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) || (ESCvar.ESC_SM3_sml > 0)))
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{
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{
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ESCvar.SMtestresult = SMRESULT_ERRSM3;
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ESCvar.SMtestresult = SMRESULT_ERRSM3;
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/* fail state change */
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/* fail state change */
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@ -759,7 +759,7 @@ uint8_t ESC_checkSM23 (uint8_t state)
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/* SM enabled and (length > 0 but SM disabled) set by master */
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/* SM enabled and (length > 0 but SM disabled) set by master */
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else if (((ESC_SM3_act & ESCREG_SYNC_ACT_ACTIVATED) > 0) &&
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else if (((ESC_SM3_act & ESCREG_SYNC_ACT_ACTIVATED) > 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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((SM->ActESC & ESCREG_SYNC_ACT_ACTIVATED) == 0) &&
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(etohs (SM->Length) > 0))
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(ESCvar.ESC_SM3_sml > 0))
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{
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{
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ESCvar.SMtestresult = SMRESULT_ERRSM3;
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ESCvar.SMtestresult = SMRESULT_ERRSM3;
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/* fail state change */
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/* fail state change */
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@ -827,15 +827,22 @@ uint8_t ESC_startinput (uint8_t state)
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{
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{
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if (ESCvar.esc_hw_interrupt_enable != NULL)
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if (ESCvar.esc_hw_interrupt_enable != NULL)
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{
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{
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if(ESCvar.dcsync > 0)
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uint32_t int_mask;
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if (ESCvar.ESC_SM2_sml == 0)
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{
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{
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ESCvar.esc_hw_interrupt_enable(ESCREG_ALEVENT_DC_SYNC0 |
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int_mask = ESCREG_ALEVENT_SM3;
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ESCREG_ALEVENT_SM2);
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}
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}
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else
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else
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{
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{
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ESCvar.esc_hw_interrupt_enable(ESCREG_ALEVENT_SM2);
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int_mask = ESCREG_ALEVENT_SM2;
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}
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}
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if (ESCvar.dcsync > 0)
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{
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int_mask |= ESCREG_ALEVENT_DC_SYNC0;
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}
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ESCvar.esc_hw_interrupt_enable (int_mask);
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}
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}
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}
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}
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}
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}
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@ -858,7 +865,8 @@ void ESC_stopinput (void)
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(ESCvar.esc_hw_interrupt_disable != NULL))
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(ESCvar.esc_hw_interrupt_disable != NULL))
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{
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{
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ESCvar.esc_hw_interrupt_disable (ESCREG_ALEVENT_DC_SYNC0 |
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ESCvar.esc_hw_interrupt_disable (ESCREG_ALEVENT_DC_SYNC0 |
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ESCREG_ALEVENT_SM2);
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ESCREG_ALEVENT_SM2 |
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ESCREG_ALEVENT_SM3);
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}
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}
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}
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}
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@ -567,15 +567,13 @@ void ESC_init (const esc_cfg_t * config)
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void ESC_interrupt_enable (uint32_t mask)
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void ESC_interrupt_enable (uint32_t mask)
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{
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{
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if (ESCREG_ALEVENT_DC_SYNC0 & mask)
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// Enable interrupt for SYNC0 or SM2 or SM3
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uint32_t user_int_mask = ESCREG_ALEVENT_DC_SYNC0 |
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ESCREG_ALEVENT_SM2 |
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ESCREG_ALEVENT_SM3;
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if (mask & user_int_mask)
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{
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{
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// Enable interrupt from SYNC0
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() | (mask & user_int_mask));
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() | ESCREG_ALEVENT_DC_SYNC0);
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}
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if (ESCREG_ALEVENT_SM2 & mask)
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{
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// Enable interrupt from SYNC0
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() | ESCREG_ALEVENT_SM2);
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}
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}
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// Set LAN9252 interrupt pin driver as push-pull active high
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// Set LAN9252 interrupt pin driver as push-pull active high
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@ -587,17 +585,18 @@ void ESC_interrupt_enable (uint32_t mask)
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void ESC_interrupt_disable (uint32_t mask)
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void ESC_interrupt_disable (uint32_t mask)
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{
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{
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if (ESCREG_ALEVENT_DC_SYNC0 & mask)
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// Enable interrupt for SYNC0 or SM2 or SM3
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uint32_t user_int_mask = ESCREG_ALEVENT_DC_SYNC0 |
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ESCREG_ALEVENT_SM2 |
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ESCREG_ALEVENT_SM3;
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if (mask & user_int_mask)
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{
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{
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// Disable interrupt from SYNC0
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// Disable interrupt from SYNC0
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() & ~(ESCREG_ALEVENT_DC_SYNC0));
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() & ~(mask & user_int_mask));
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}
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if (ESCREG_ALEVENT_SM2 & mask)
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{
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// Disable interrupt from SM2
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ESC_ALeventmaskwrite(ESC_ALeventmaskread() & ~(ESCREG_ALEVENT_SM2));
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}
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}
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// Disable LAN9252 interrupt
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// Disable LAN9252 interrupt
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bcm2835_spi_write_32(ESC_CMD_INT_EN, 0x00000000);
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bcm2835_spi_write_32(ESC_CMD_INT_EN, 0x00000000);
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}
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}
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@ -242,8 +242,8 @@ static void ecat_isr (void * arg)
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CC_ATOMIC_SET(ESCvar.ALevent, etohl(ecat0->AL_EVENT_REQ));
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CC_ATOMIC_SET(ESCvar.ALevent, etohl(ecat0->AL_EVENT_REQ));
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CC_ATOMIC_SET(ESCvar.Time, etohl(ecat0->READMode_DC_SYS_TIME[0]));
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CC_ATOMIC_SET(ESCvar.Time, etohl(ecat0->READMode_DC_SYS_TIME[0]));
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/* Handle SM2 interrupt */
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/* Handle SM2 & SM3 interrupt */
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if(ESCvar.ALevent & ESCREG_ALEVENT_SM2)
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if(ESCvar.ALevent & (ESCREG_ALEVENT_SM2 | ESCREG_ALEVENT_SM3))
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{
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{
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/* Is DC active or not */
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/* Is DC active or not */
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if(ESCvar.dcsync == 0)
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if(ESCvar.dcsync == 0)
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@ -301,7 +301,7 @@ void PDI_Isr(void)
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alevent = bsp_read_word_isr(escHwPruIcssHandle,ESCREG_ALEVENT);
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alevent = bsp_read_word_isr(escHwPruIcssHandle,ESCREG_ALEVENT);
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CC_ATOMIC_SET(ESCvar.ALevent, etohs(alevent));
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CC_ATOMIC_SET(ESCvar.ALevent, etohs(alevent));
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if(ESCvar.ALevent & ESCREG_ALEVENT_SM2)
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if(ESCvar.ALevent & (ESCREG_ALEVENT_SM2 & ESCREG_ALEVENT_SM3))
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{
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{
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DIG_process(DIG_PROCESS_OUTPUTS_FLAG |
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DIG_process(DIG_PROCESS_OUTPUTS_FLAG |
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DIG_PROCESS_APP_HOOK_FLAG |
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DIG_PROCESS_APP_HOOK_FLAG |
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