2020-04-23 20:30:50 +02:00
|
|
|
/*
|
|
|
|
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
|
|
|
|
*
|
|
|
|
* Copyright (c) 2020 Western Digital
|
|
|
|
*
|
|
|
|
* Provides a board compatible with the OpenTitan FPGA platform:
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
* more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License along with
|
|
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "qemu/osdep.h"
|
|
|
|
#include "hw/riscv/opentitan.h"
|
|
|
|
#include "qapi/error.h"
|
|
|
|
#include "hw/boards.h"
|
|
|
|
#include "hw/misc/unimp.h"
|
|
|
|
#include "hw/riscv/boot.h"
|
2020-06-10 01:08:29 +02:00
|
|
|
#include "qemu/units.h"
|
2020-04-24 03:40:57 +02:00
|
|
|
#include "sysemu/sysemu.h"
|
2020-04-23 20:30:50 +02:00
|
|
|
|
2021-02-20 15:48:04 +01:00
|
|
|
static const MemMapEntry ibex_memmap[] = {
|
2020-08-25 21:20:03 +02:00
|
|
|
[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
|
|
|
|
[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
|
|
|
|
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
|
2020-12-15 02:56:54 +01:00
|
|
|
[IBEX_DEV_UART] = { 0x40000000, 0x1000 },
|
|
|
|
[IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
|
|
|
|
[IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
|
|
|
|
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
|
|
|
|
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
|
2021-06-18 09:28:01 +02:00
|
|
|
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
|
2020-12-15 02:56:54 +01:00
|
|
|
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
|
|
|
|
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
|
|
|
|
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
|
|
|
|
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
|
|
|
|
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
|
|
|
|
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
|
|
|
|
[IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
|
|
|
|
[IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 },
|
|
|
|
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
|
|
|
|
[IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
|
|
|
|
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
|
|
|
|
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
|
|
|
|
[IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
|
|
|
|
[IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
|
|
|
|
[IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
|
|
|
|
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
|
|
|
|
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
|
|
|
|
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
|
|
|
|
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
|
|
|
|
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
|
|
|
|
[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
|
2020-04-23 20:30:50 +02:00
|
|
|
};
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void opentitan_board_init(MachineState *machine)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
2021-02-20 15:48:04 +01:00
|
|
|
const MemMapEntry *memmap = ibex_memmap;
|
2020-04-23 20:30:50 +02:00
|
|
|
OpenTitanState *s = g_new0(OpenTitanState, 1);
|
|
|
|
MemoryRegion *sys_mem = get_system_memory();
|
|
|
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
|
|
|
|
|
|
|
/* Initialize SoC */
|
|
|
|
object_initialize_child(OBJECT(machine), "soc", &s->soc,
|
qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 07:32:25 +02:00
|
|
|
TYPE_RISCV_IBEX_SOC);
|
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 07:32:45 +02:00
|
|
|
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
|
2020-04-23 20:30:50 +02:00
|
|
|
|
|
|
|
memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_RAM].size, &error_fatal);
|
2020-04-23 20:30:50 +02:00
|
|
|
memory_region_add_subregion(sys_mem,
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_RAM].base, main_mem);
|
2020-04-23 20:30:50 +02:00
|
|
|
|
|
|
|
if (machine->firmware) {
|
2020-08-25 21:20:03 +02:00
|
|
|
riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
|
2020-04-23 20:30:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (machine->kernel_filename) {
|
2020-10-14 02:17:33 +02:00
|
|
|
riscv_load_kernel(machine->kernel_filename,
|
|
|
|
memmap[IBEX_DEV_RAM].base, NULL);
|
2020-04-23 20:30:50 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void opentitan_machine_init(MachineClass *mc)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
|
|
|
mc->desc = "RISC-V Board compatible with OpenTitan";
|
2020-06-08 16:17:31 +02:00
|
|
|
mc->init = opentitan_board_init;
|
2020-04-23 20:30:50 +02:00
|
|
|
mc->max_cpus = 1;
|
|
|
|
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
|
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
DEFINE_MACHINE("opentitan", opentitan_machine_init)
|
2020-04-23 20:30:50 +02:00
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void lowrisc_ibex_soc_init(Object *obj)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
|
|
|
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
|
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
|
|
|
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
|
2020-04-24 03:40:57 +02:00
|
|
|
|
|
|
|
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
|
2020-04-23 23:08:45 +02:00
|
|
|
|
|
|
|
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
|
2021-06-18 09:28:01 +02:00
|
|
|
|
|
|
|
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
|
2020-04-23 20:30:50 +02:00
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
2021-02-20 15:48:04 +01:00
|
|
|
const MemMapEntry *memmap = ibex_memmap;
|
2020-04-23 20:30:50 +02:00
|
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
|
|
|
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
|
|
|
|
MemoryRegion *sys_mem = get_system_memory();
|
|
|
|
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
|
2020-04-23 20:30:50 +02:00
|
|
|
&error_abort);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
|
2020-04-23 20:30:50 +02:00
|
|
|
&error_abort);
|
2021-04-20 10:00:08 +02:00
|
|
|
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
|
2020-04-23 20:30:50 +02:00
|
|
|
|
|
|
|
/* Boot ROM */
|
|
|
|
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_ROM].size, &error_fatal);
|
2020-04-23 20:30:50 +02:00
|
|
|
memory_region_add_subregion(sys_mem,
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_ROM].base, &s->rom);
|
2020-04-23 20:30:50 +02:00
|
|
|
|
|
|
|
/* Flash memory */
|
|
|
|
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_FLASH].size, &error_fatal);
|
|
|
|
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
|
2020-04-23 20:30:50 +02:00
|
|
|
&s->flash_mem);
|
|
|
|
|
2020-04-24 03:40:57 +02:00
|
|
|
/* PLIC */
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
|
2020-04-24 03:40:57 +02:00
|
|
|
return;
|
|
|
|
}
|
2020-08-25 21:20:03 +02:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
|
2020-04-24 03:40:57 +02:00
|
|
|
|
2020-04-23 23:08:45 +02:00
|
|
|
/* UART */
|
|
|
|
qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
|
2020-04-23 23:08:45 +02:00
|
|
|
return;
|
|
|
|
}
|
2020-08-25 21:20:03 +02:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
|
2020-04-23 23:08:45 +02:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
|
|
|
|
0, qdev_get_gpio_in(DEVICE(&s->plic),
|
2021-03-31 17:00:11 +02:00
|
|
|
IBEX_UART0_TX_WATERMARK_IRQ));
|
2020-04-23 23:08:45 +02:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
|
|
|
|
1, qdev_get_gpio_in(DEVICE(&s->plic),
|
2021-03-31 17:00:11 +02:00
|
|
|
IBEX_UART0_RX_WATERMARK_IRQ));
|
2020-04-23 23:08:45 +02:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
|
|
|
|
2, qdev_get_gpio_in(DEVICE(&s->plic),
|
2021-03-31 17:00:11 +02:00
|
|
|
IBEX_UART0_TX_EMPTY_IRQ));
|
2020-04-23 23:08:45 +02:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
|
|
|
|
3, qdev_get_gpio_in(DEVICE(&s->plic),
|
2021-03-31 17:00:11 +02:00
|
|
|
IBEX_UART0_RX_OVERFLOW_IRQ));
|
2020-04-23 23:08:45 +02:00
|
|
|
|
2021-06-18 09:28:01 +02:00
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
|
|
|
|
0, qdev_get_gpio_in(DEVICE(&s->plic),
|
|
|
|
IBEX_TIMER_TIMEREXPIRED0_0));
|
|
|
|
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.spi",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
|
2020-12-15 02:56:54 +01:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
|
|
|
|
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
|
|
|
|
memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
|
|
|
|
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
|
|
|
|
memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
|
2020-12-15 02:56:54 +01:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
|
|
|
|
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
|
|
|
|
memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
|
|
|
|
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
|
|
|
|
memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.aes",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
|
2020-12-15 02:56:54 +01:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.kmac",
|
|
|
|
memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
|
|
|
|
memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.csrng",
|
|
|
|
memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.entropy",
|
|
|
|
memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.edn0",
|
|
|
|
memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
|
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.edn1",
|
|
|
|
memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
|
2020-08-25 21:20:03 +02:00
|
|
|
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
|
2020-12-15 02:56:54 +01:00
|
|
|
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
|
|
|
|
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
|
2020-04-23 20:30:50 +02:00
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
dc->realize = lowrisc_ibex_soc_realize;
|
2020-04-23 20:30:50 +02:00
|
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
|
|
dc->user_creatable = false;
|
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static const TypeInfo lowrisc_ibex_soc_type_info = {
|
2020-04-23 20:30:50 +02:00
|
|
|
.name = TYPE_RISCV_IBEX_SOC,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(LowRISCIbexSoCState),
|
2020-06-08 16:17:31 +02:00
|
|
|
.instance_init = lowrisc_ibex_soc_init,
|
|
|
|
.class_init = lowrisc_ibex_soc_class_init,
|
2020-04-23 20:30:50 +02:00
|
|
|
};
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
static void lowrisc_ibex_soc_register_types(void)
|
2020-04-23 20:30:50 +02:00
|
|
|
{
|
2020-06-08 16:17:31 +02:00
|
|
|
type_register_static(&lowrisc_ibex_soc_type_info);
|
2020-04-23 20:30:50 +02:00
|
|
|
}
|
|
|
|
|
2020-06-08 16:17:31 +02:00
|
|
|
type_init(lowrisc_ibex_soc_register_types)
|