2008-02-03 03:20:18 +01:00
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/*
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* QEMU e1000 emulation
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*
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2009-12-23 16:05:21 +01:00
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* Software developer's manual:
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* http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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*
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2008-02-03 03:20:18 +01:00
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2008-02-03 03:20:18 +01:00
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*/
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2016-01-26 19:17:11 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2009-10-22 18:49:03 +02:00
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#include "net/checksum.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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2013-09-12 10:47:37 +02:00
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#include "qemu/iov.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2014-12-01 19:06:52 +01:00
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#include "qemu/range.h"
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2008-02-03 03:20:18 +01:00
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2016-06-01 10:23:44 +02:00
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#include "e1000x_common.h"
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2018-10-16 11:40:45 +02:00
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#include "trace.h"
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2008-02-03 03:20:18 +01:00
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2015-11-11 14:52:46 +01:00
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static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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2017-03-22 01:05:44 +01:00
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/* #define E1000_DEBUG */
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2008-02-03 03:20:18 +01:00
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2010-06-14 17:05:17 +02:00
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#ifdef E1000_DEBUG
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2008-02-03 03:20:18 +01:00
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enum {
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2015-11-11 14:52:39 +01:00
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DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
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DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
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DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
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2012-03-22 11:02:16 +01:00
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DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
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2008-02-03 03:20:18 +01:00
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};
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2015-11-11 14:52:39 +01:00
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#define DBGBIT(x) (1<<DEBUG_##x)
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2008-02-03 03:20:18 +01:00
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static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
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2015-11-11 14:52:39 +01:00
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#define DBGOUT(what, fmt, ...) do { \
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2008-02-03 03:20:18 +01:00
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if (debugflags & DBGBIT(what)) \
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2009-05-13 20:09:29 +02:00
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fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
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2008-02-03 03:20:18 +01:00
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} while (0)
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#else
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2015-11-11 14:52:39 +01:00
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#define DBGOUT(what, fmt, ...) do {} while (0)
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2008-02-03 03:20:18 +01:00
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#endif
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#define IOPORT_SIZE 0x40
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2008-03-10 01:02:10 +01:00
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#define PNPMMIO_SIZE 0x20000
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2010-09-18 22:43:45 +02:00
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#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
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2008-02-03 03:20:18 +01:00
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2013-09-12 10:47:37 +02:00
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#define MAXIMUM_ETHERNET_HDR_LEN (14+4)
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2008-02-03 03:20:18 +01:00
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/*
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* HW models:
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2014-06-02 15:33:27 +02:00
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* E1000_DEV_ID_82540EM works with Windows, Linux, and OS X <= 10.8
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2008-02-03 03:20:18 +01:00
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* E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
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2014-06-02 15:33:27 +02:00
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* E1000_DEV_ID_82545EM_COPPER works with Linux and OS X >= 10.6
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2008-02-03 03:20:18 +01:00
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* Others never tested
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*/
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typedef struct E1000State_st {
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2013-06-30 12:55:52 +02:00
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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2009-11-25 19:49:12 +01:00
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NICState *nic;
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2009-10-21 15:25:31 +02:00
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NICConf conf;
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2011-08-08 15:09:08 +02:00
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MemoryRegion mmio;
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MemoryRegion io;
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2008-02-03 03:20:18 +01:00
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uint32_t mac_reg[0x8000];
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uint16_t phy_reg[0x20];
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uint16_t eeprom_data[64];
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uint32_t rxbuf_size;
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uint32_t rxbuf_min_shift;
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struct e1000_tx {
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unsigned char header[256];
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2008-11-21 17:25:17 +01:00
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unsigned char vlan_header[4];
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2009-11-19 19:44:55 +01:00
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/* Fields vlan and data must not be reordered or separated. */
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2008-11-21 17:25:17 +01:00
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unsigned char vlan[4];
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2008-02-03 03:20:18 +01:00
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unsigned char data[0x10000];
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uint16_t size;
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2008-11-21 17:25:17 +01:00
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unsigned char vlan_needed;
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2017-11-15 00:23:33 +01:00
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unsigned char sum_needed;
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bool cptse;
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2016-06-01 10:23:44 +02:00
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e1000x_txd_props props;
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e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
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e1000x_txd_props tso_props;
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2008-02-03 03:20:18 +01:00
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uint16_t tso_frames;
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} tx;
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struct {
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2015-11-11 14:52:39 +01:00
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uint32_t val_in; /* shifted in from guest driver */
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2008-02-03 03:20:18 +01:00
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uint16_t bitnum_in;
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uint16_t bitnum_out;
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uint16_t reading;
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uint32_t old_eecd;
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} eecd_state;
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2012-03-22 11:02:24 +01:00
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QEMUTimer *autoneg_timer;
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2013-02-14 18:11:27 +01:00
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e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
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QEMUTimer *mit_timer; /* Mitigation timer. */
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bool mit_timer_on; /* Mitigation timer is running. */
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bool mit_irq_level; /* Tracks interrupt pin level. */
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uint32_t mit_ide; /* Tracks E1000_TXD_CMD_IDE bit. */
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e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
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QEMUTimer *flush_queue_timer;
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2013-02-14 18:11:27 +01:00
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/* Compatibility flags for migration to/from qemu 1.3.0 and older */
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#define E1000_FLAG_AUTONEG_BIT 0
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e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
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#define E1000_FLAG_MIT_BIT 1
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2015-11-11 14:52:40 +01:00
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#define E1000_FLAG_MAC_BIT 2
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2018-03-28 18:36:27 +02:00
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#define E1000_FLAG_TSO_BIT 3
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2013-02-14 18:11:27 +01:00
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#define E1000_FLAG_AUTONEG (1 << E1000_FLAG_AUTONEG_BIT)
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
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#define E1000_FLAG_MIT (1 << E1000_FLAG_MIT_BIT)
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2015-11-11 14:52:40 +01:00
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#define E1000_FLAG_MAC (1 << E1000_FLAG_MAC_BIT)
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2018-03-28 18:36:27 +02:00
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#define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT)
|
2013-02-14 18:11:27 +01:00
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uint32_t compat_flags;
|
2018-03-28 18:36:26 +02:00
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bool received_tx_tso;
|
2018-03-28 18:36:29 +02:00
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bool use_tso_for_migration;
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2018-03-28 18:36:28 +02:00
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e1000x_txd_props mig_props;
|
2008-02-03 03:20:18 +01:00
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} E1000State;
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e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
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|
|
#define chkflag(x) (s->compat_flags & E1000_FLAG_##x)
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|
2014-06-02 15:33:27 +02:00
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|
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typedef struct E1000BaseClass {
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PCIDeviceClass parent_class;
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uint16_t phy_id2;
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} E1000BaseClass;
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#define TYPE_E1000_BASE "e1000-base"
|
2013-06-24 08:50:30 +02:00
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#define E1000(obj) \
|
2014-06-02 15:33:27 +02:00
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|
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OBJECT_CHECK(E1000State, (obj), TYPE_E1000_BASE)
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|
|
|
|
|
#define E1000_DEVICE_CLASS(klass) \
|
|
|
|
OBJECT_CLASS_CHECK(E1000BaseClass, (klass), TYPE_E1000_BASE)
|
|
|
|
#define E1000_DEVICE_GET_CLASS(obj) \
|
|
|
|
OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
|
2013-06-24 08:50:30 +02:00
|
|
|
|
2012-03-22 11:02:07 +01:00
|
|
|
static void
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000_link_up(E1000State *s)
|
2012-03-22 11:02:07 +01:00
|
|
|
{
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_update_regs_on_link_up(s->mac_reg, s->phy_reg);
|
|
|
|
|
|
|
|
/* E1000_STATUS_LU is tested by e1000_can_receive() */
|
|
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
2012-03-22 11:02:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000_autoneg_done(E1000State *s)
|
2012-03-22 11:02:07 +01:00
|
|
|
{
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_update_regs_on_autoneg_done(s->mac_reg, s->phy_reg);
|
2015-06-25 11:18:05 +02:00
|
|
|
|
|
|
|
/* E1000_STATUS_LU is tested by e1000_can_receive() */
|
|
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
2012-03-22 11:02:07 +01:00
|
|
|
}
|
|
|
|
|
2014-08-06 20:07:10 +02:00
|
|
|
static bool
|
|
|
|
have_autoneg(E1000State *s)
|
|
|
|
{
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
return chkflag(AUTONEG) && (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN);
|
2014-08-06 20:07:10 +02:00
|
|
|
}
|
|
|
|
|
2012-03-22 11:02:24 +01:00
|
|
|
static void
|
|
|
|
set_phy_ctrl(E1000State *s, int index, uint16_t val)
|
|
|
|
{
|
2014-08-06 20:07:10 +02:00
|
|
|
/* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
|
|
|
|
s->phy_reg[PHY_CTRL] = val & ~(0x3f |
|
|
|
|
MII_CR_RESET |
|
|
|
|
MII_CR_RESTART_AUTO_NEG);
|
|
|
|
|
2013-02-14 18:11:27 +01:00
|
|
|
/*
|
|
|
|
* QEMU 1.3 does not support link auto-negotiation emulation, so if we
|
|
|
|
* migrate during auto negotiation, after migration the link will be
|
|
|
|
* down.
|
|
|
|
*/
|
2014-08-06 20:07:10 +02:00
|
|
|
if (have_autoneg(s) && (val & MII_CR_RESTART_AUTO_NEG)) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer);
|
2012-03-22 11:02:24 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
|
|
|
|
[PHY_CTRL] = set_phy_ctrl,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
|
2008-10-02 20:24:21 +02:00
|
|
|
static const char phy_regcap[0x20] = {
|
2015-11-11 14:52:39 +01:00
|
|
|
[PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
|
|
|
|
[PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
|
|
|
|
[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
|
|
|
|
[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
|
|
|
|
[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
|
|
|
|
[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
|
2014-06-19 17:55:34 +02:00
|
|
|
[PHY_AUTONEG_EXP] = PHY_R,
|
2008-02-03 03:20:18 +01:00
|
|
|
};
|
|
|
|
|
2014-06-02 15:33:27 +02:00
|
|
|
/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */
|
2012-02-12 14:11:53 +01:00
|
|
|
static const uint16_t phy_reg_init[] = {
|
2015-11-11 14:52:39 +01:00
|
|
|
[PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
|
2014-08-06 20:07:11 +02:00
|
|
|
MII_CR_FULL_DUPLEX |
|
|
|
|
MII_CR_AUTO_NEG_EN,
|
|
|
|
|
|
|
|
[PHY_STATUS] = MII_SR_EXTENDED_CAPS |
|
|
|
|
MII_SR_LINK_STATUS | /* link initially up */
|
|
|
|
MII_SR_AUTONEG_CAPS |
|
|
|
|
/* MII_SR_AUTONEG_COMPLETE: initially NOT completed */
|
|
|
|
MII_SR_PREAMBLE_SUPPRESS |
|
|
|
|
MII_SR_EXTENDED_STATUS |
|
|
|
|
MII_SR_10T_HD_CAPS |
|
|
|
|
MII_SR_10T_FD_CAPS |
|
|
|
|
MII_SR_100X_HD_CAPS |
|
|
|
|
MII_SR_100X_FD_CAPS,
|
|
|
|
|
|
|
|
[PHY_ID1] = 0x141,
|
|
|
|
/* [PHY_ID2] configured per DevId, from e1000_reset() */
|
|
|
|
[PHY_AUTONEG_ADV] = 0xde1,
|
|
|
|
[PHY_LP_ABILITY] = 0x1e0,
|
|
|
|
[PHY_1000T_CTRL] = 0x0e00,
|
|
|
|
[PHY_1000T_STATUS] = 0x3c00,
|
|
|
|
[M88E1000_PHY_SPEC_CTRL] = 0x360,
|
2012-02-12 14:11:53 +01:00
|
|
|
[M88E1000_PHY_SPEC_STATUS] = 0xac00,
|
2014-08-06 20:07:11 +02:00
|
|
|
[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60,
|
2012-02-12 14:11:53 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static const uint32_t mac_reg_init[] = {
|
2015-11-11 14:52:39 +01:00
|
|
|
[PBA] = 0x00100030,
|
|
|
|
[LEDCTL] = 0x602,
|
|
|
|
[CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
|
2012-02-12 14:11:53 +01:00
|
|
|
E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
|
2015-11-11 14:52:39 +01:00
|
|
|
[STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
|
2012-02-12 14:11:53 +01:00
|
|
|
E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
|
|
|
|
E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
|
|
|
|
E1000_STATUS_LU,
|
2015-11-11 14:52:39 +01:00
|
|
|
[MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
|
2012-02-12 14:11:53 +01:00
|
|
|
E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
|
|
|
|
E1000_MANC_RMCP_EN,
|
|
|
|
};
|
|
|
|
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
/* Helper function, *curr == 0 means the value is not set */
|
|
|
|
static inline void
|
|
|
|
mit_update_delay(uint32_t *curr, uint32_t value)
|
|
|
|
{
|
|
|
|
if (value && (*curr == 0 || value < *curr)) {
|
|
|
|
*curr = value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static void
|
|
|
|
set_interrupt_cause(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
2013-06-30 12:55:52 +02:00
|
|
|
PCIDevice *d = PCI_DEVICE(s);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
uint32_t pending_ints;
|
|
|
|
uint32_t mit_delay;
|
2013-06-30 12:55:52 +02:00
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
s->mac_reg[ICR] = val;
|
2013-01-09 22:50:00 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure ICR and ICS registers have the same value.
|
|
|
|
* The spec says that the ICS register is write-only. However in practice,
|
|
|
|
* on real hardware ICS is readable, and for reads it has the same value as
|
|
|
|
* ICR (except that ICS does not have the clear on read behaviour of ICR).
|
|
|
|
*
|
|
|
|
* The VxWorks PRO/1000 driver uses this behaviour.
|
|
|
|
*/
|
2009-07-29 19:22:55 +02:00
|
|
|
s->mac_reg[ICS] = val;
|
2013-01-09 22:50:00 +01:00
|
|
|
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]);
|
|
|
|
if (!s->mit_irq_level && pending_ints) {
|
|
|
|
/*
|
|
|
|
* Here we detect a potential raising edge. We postpone raising the
|
|
|
|
* interrupt line if we are inside the mitigation delay window
|
|
|
|
* (s->mit_timer_on == 1).
|
|
|
|
* We provide a partial implementation of interrupt mitigation,
|
|
|
|
* emulating only RADV, TADV and ITR (lower 16 bits, 1024ns units for
|
|
|
|
* RADV and TADV, 256ns units for ITR). RDTR is only used to enable
|
|
|
|
* RADV; relative timers based on TIDV and RDTR are not implemented.
|
|
|
|
*/
|
|
|
|
if (s->mit_timer_on) {
|
|
|
|
return;
|
|
|
|
}
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
if (chkflag(MIT)) {
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
/* Compute the next mitigation delay according to pending
|
|
|
|
* interrupts and the current values of RADV (provided
|
|
|
|
* RDTR!=0), TADV and ITR.
|
|
|
|
* Then rearm the timer.
|
|
|
|
*/
|
|
|
|
mit_delay = 0;
|
|
|
|
if (s->mit_ide &&
|
|
|
|
(pending_ints & (E1000_ICR_TXQE | E1000_ICR_TXDW))) {
|
|
|
|
mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4);
|
|
|
|
}
|
|
|
|
if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) {
|
|
|
|
mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4);
|
|
|
|
}
|
|
|
|
mit_update_delay(&mit_delay, s->mac_reg[ITR]);
|
|
|
|
|
2016-03-17 08:37:57 +01:00
|
|
|
/*
|
|
|
|
* According to e1000 SPEC, the Ethernet controller guarantees
|
|
|
|
* a maximum observable interrupt rate of 7813 interrupts/sec.
|
|
|
|
* Thus if mit_delay < 500 then the delay should be set to the
|
|
|
|
* minimum delay possible which is 500.
|
|
|
|
*/
|
|
|
|
mit_delay = (mit_delay < 500) ? 500 : mit_delay;
|
|
|
|
|
2016-05-29 08:37:25 +02:00
|
|
|
s->mit_timer_on = 1;
|
|
|
|
timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
|
|
|
mit_delay * 256);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
s->mit_ide = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
s->mit_irq_level = (pending_ints != 0);
|
2013-10-07 09:36:39 +02:00
|
|
|
pci_set_irq(d, s->mit_irq_level);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
e1000_mit_timer(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
|
|
|
|
s->mit_timer_on = 0;
|
|
|
|
/* Call set_interrupt_cause to update the irq level (if necessary). */
|
|
|
|
set_interrupt_cause(s, 0, s->mac_reg[ICR]);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_ics(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
|
|
|
|
s->mac_reg[IMS]);
|
|
|
|
set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
|
|
|
|
}
|
|
|
|
|
2014-06-19 17:55:35 +02:00
|
|
|
static void
|
|
|
|
e1000_autoneg_timer(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
if (!qemu_get_queue(s->nic)->link_down) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000_autoneg_done(s);
|
2014-06-19 17:55:35 +02:00
|
|
|
set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-02-12 14:11:53 +01:00
|
|
|
static void e1000_reset(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *d = opaque;
|
2014-06-02 15:33:27 +02:00
|
|
|
E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d);
|
2012-10-31 19:15:39 +01:00
|
|
|
uint8_t *macaddr = d->conf.macaddr.a;
|
2012-02-12 14:11:53 +01:00
|
|
|
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_del(d->autoneg_timer);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
timer_del(d->mit_timer);
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
timer_del(d->flush_queue_timer);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
d->mit_timer_on = 0;
|
|
|
|
d->mit_irq_level = 0;
|
|
|
|
d->mit_ide = 0;
|
2012-02-12 14:11:53 +01:00
|
|
|
memset(d->phy_reg, 0, sizeof d->phy_reg);
|
|
|
|
memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
|
2014-06-02 15:33:27 +02:00
|
|
|
d->phy_reg[PHY_ID2] = edc->phy_id2;
|
2012-02-12 14:11:53 +01:00
|
|
|
memset(d->mac_reg, 0, sizeof d->mac_reg);
|
|
|
|
memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
|
|
|
|
d->rxbuf_min_shift = 1;
|
|
|
|
memset(&d->tx, 0, sizeof d->tx);
|
|
|
|
|
2013-01-30 12:12:22 +01:00
|
|
|
if (qemu_get_queue(d->nic)->link_down) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_update_regs_on_link_down(d->mac_reg, d->phy_reg);
|
2012-02-12 14:11:53 +01:00
|
|
|
}
|
2012-10-31 19:15:39 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr);
|
2012-02-12 14:11:53 +01:00
|
|
|
}
|
|
|
|
|
2009-05-23 11:21:33 +02:00
|
|
|
static void
|
|
|
|
set_ctrl(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
/* RST is self clearing */
|
|
|
|
s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
|
|
|
|
}
|
|
|
|
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
static void
|
|
|
|
e1000_flush_queue_timer(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
|
|
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static void
|
|
|
|
set_rx_control(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[RCTL] = val;
|
2016-06-01 10:23:44 +02:00
|
|
|
s->rxbuf_size = e1000x_rxbufsize(val);
|
2008-02-03 03:20:18 +01:00
|
|
|
s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
|
|
|
|
DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
|
|
|
|
s->mac_reg[RCTL]);
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
timer_mod(s->flush_queue_timer,
|
|
|
|
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_mdic(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t data = val & E1000_MDIC_DATA_MASK;
|
|
|
|
uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
|
|
|
|
|
|
|
|
if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
|
|
|
|
val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
|
|
|
|
else if (val & E1000_MDIC_OP_READ) {
|
|
|
|
DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
|
|
|
|
if (!(phy_regcap[addr] & PHY_R)) {
|
|
|
|
DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
|
|
|
|
val |= E1000_MDIC_ERROR;
|
|
|
|
} else
|
|
|
|
val = (val ^ data) | s->phy_reg[addr];
|
|
|
|
} else if (val & E1000_MDIC_OP_WRITE) {
|
|
|
|
DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
|
|
|
|
if (!(phy_regcap[addr] & PHY_W)) {
|
|
|
|
DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
|
|
|
|
val |= E1000_MDIC_ERROR;
|
2012-03-22 11:02:24 +01:00
|
|
|
} else {
|
|
|
|
if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
|
|
|
|
phyreg_writeops[addr](s, index, data);
|
2014-08-06 20:07:10 +02:00
|
|
|
} else {
|
|
|
|
s->phy_reg[addr] = data;
|
2012-03-22 11:02:24 +01:00
|
|
|
}
|
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
s->mac_reg[MDIC] = val | E1000_MDIC_READY;
|
2012-03-22 11:01:50 +01:00
|
|
|
|
|
|
|
if (val & E1000_MDIC_INT_EN) {
|
|
|
|
set_ics(s, 0, E1000_ICR_MDAC);
|
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
get_eecd(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
|
|
|
|
|
|
|
|
DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
|
|
|
|
s->eecd_state.bitnum_out, s->eecd_state.reading);
|
|
|
|
if (!s->eecd_state.reading ||
|
|
|
|
((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
|
|
|
|
((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
|
|
|
|
ret |= E1000_EECD_DO;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_eecd(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t oldval = s->eecd_state.old_eecd;
|
|
|
|
|
|
|
|
s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
|
|
|
|
E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
|
2015-11-11 14:52:39 +01:00
|
|
|
if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */
|
|
|
|
s->eecd_state.val_in = 0;
|
|
|
|
s->eecd_state.bitnum_in = 0;
|
|
|
|
s->eecd_state.bitnum_out = 0;
|
|
|
|
s->eecd_state.reading = 0;
|
2010-07-10 16:03:45 +02:00
|
|
|
}
|
2015-11-11 14:52:39 +01:00
|
|
|
if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */
|
2008-02-03 03:20:18 +01:00
|
|
|
return;
|
2015-11-11 14:52:39 +01:00
|
|
|
}
|
|
|
|
if (!(E1000_EECD_SK & val)) { /* falling edge */
|
2008-02-03 03:20:18 +01:00
|
|
|
s->eecd_state.bitnum_out++;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
s->eecd_state.val_in <<= 1;
|
|
|
|
if (val & E1000_EECD_DI)
|
|
|
|
s->eecd_state.val_in |= 1;
|
|
|
|
if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
|
|
|
|
s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
|
|
|
|
s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
|
|
|
|
EEPROM_READ_OPCODE_MICROWIRE);
|
|
|
|
}
|
|
|
|
DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
|
|
|
|
s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
|
|
|
|
s->eecd_state.reading);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
flash_eerd_read(E1000State *s, int x)
|
|
|
|
{
|
|
|
|
unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
|
|
|
|
|
2009-07-29 19:22:55 +02:00
|
|
|
if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
|
|
|
|
return (s->mac_reg[EERD]);
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
|
2009-07-29 19:22:55 +02:00
|
|
|
return (E1000_EEPROM_RW_REG_DONE | r);
|
|
|
|
|
|
|
|
return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
|
|
|
|
E1000_EEPROM_RW_REG_DONE | r);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
|
|
|
|
{
|
2008-07-29 21:41:19 +02:00
|
|
|
uint32_t sum;
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
if (cse && cse < n)
|
|
|
|
n = cse + 1;
|
2008-07-29 21:41:19 +02:00
|
|
|
if (sloc < n-1) {
|
|
|
|
sum = net_checksum_add(n-css, data+css);
|
2017-11-16 15:06:06 +01:00
|
|
|
stw_be_p(data + sloc, net_checksum_finish_nozero(sum));
|
2008-07-29 21:41:19 +02:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2015-11-11 14:52:46 +01:00
|
|
|
static inline void
|
|
|
|
inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr)
|
|
|
|
{
|
|
|
|
if (!memcmp(arr, bcast, sizeof bcast)) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, BPTC);
|
2015-11-11 14:52:46 +01:00
|
|
|
} else if (arr[0] & 1) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, MPTC);
|
2015-11-11 14:52:46 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-22 11:01:59 +01:00
|
|
|
static void
|
|
|
|
e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
|
|
|
|
{
|
2015-11-11 14:52:46 +01:00
|
|
|
static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
|
|
|
|
PTC1023, PTC1522 };
|
|
|
|
|
2013-01-30 12:12:22 +01:00
|
|
|
NetClientState *nc = qemu_get_queue(s->nic);
|
2012-03-22 11:01:59 +01:00
|
|
|
if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
|
2013-01-30 12:12:22 +01:00
|
|
|
nc->info->receive(nc, buf, size);
|
2012-03-22 11:01:59 +01:00
|
|
|
} else {
|
2013-01-30 12:12:22 +01:00
|
|
|
qemu_send_packet(nc, buf, size);
|
2012-03-22 11:01:59 +01:00
|
|
|
}
|
2015-11-11 14:52:46 +01:00
|
|
|
inc_tx_bcast_or_mcast_count(s, buf);
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_increase_size_stats(s->mac_reg, PTCregs, size);
|
2012-03-22 11:01:59 +01:00
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static void
|
|
|
|
xmit_seg(E1000State *s)
|
|
|
|
{
|
2016-06-16 19:17:26 +02:00
|
|
|
uint16_t len;
|
2015-11-11 14:52:44 +01:00
|
|
|
unsigned int frames = s->tx.tso_frames, css, sofar;
|
2008-02-03 03:20:18 +01:00
|
|
|
struct e1000_tx *tp = &s->tx;
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
struct e1000x_txd_props *props = tp->cptse ? &tp->tso_props : &tp->props;
|
2008-02-03 03:20:18 +01:00
|
|
|
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (tp->cptse) {
|
|
|
|
css = props->ipcss;
|
2008-02-03 03:20:18 +01:00
|
|
|
DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
|
|
|
|
frames, tp->size, css);
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (props->ip) { /* IPv4 */
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(tp->data+css+2, tp->size - css);
|
|
|
|
stw_be_p(tp->data+css+4,
|
2016-06-16 19:17:26 +02:00
|
|
|
lduw_be_p(tp->data + css + 4) + frames);
|
2015-11-11 14:52:39 +01:00
|
|
|
} else { /* IPv6 */
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(tp->data+css+4, tp->size - css);
|
2015-11-11 14:52:39 +01:00
|
|
|
}
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
css = props->tucss;
|
2008-02-03 03:20:18 +01:00
|
|
|
len = tp->size - css;
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", props->tcp, css, len);
|
|
|
|
if (props->tcp) {
|
|
|
|
sofar = frames * props->mss;
|
2013-11-05 17:38:35 +01:00
|
|
|
stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (props->paylen - sofar > props->mss) {
|
2015-11-11 14:52:39 +01:00
|
|
|
tp->data[css + 13] &= ~9; /* PSH, FIN */
|
2015-11-11 14:52:46 +01:00
|
|
|
} else if (frames) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, TSCTC);
|
2015-11-11 14:52:46 +01:00
|
|
|
}
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
} else { /* UDP */
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(tp->data+css+4, len);
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
}
|
2017-11-15 00:23:33 +01:00
|
|
|
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
|
2010-11-05 21:52:08 +01:00
|
|
|
unsigned int phsum;
|
2008-02-03 03:20:18 +01:00
|
|
|
// add pseudo-header length before checksum calculation
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
void *sp = tp->data + props->tucso;
|
2016-06-16 19:17:26 +02:00
|
|
|
|
|
|
|
phsum = lduw_be_p(sp) + len;
|
2010-11-05 21:52:08 +01:00
|
|
|
phsum = (phsum >> 16) + (phsum & 0xffff);
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(sp, phsum);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
tp->tso_frames++;
|
|
|
|
}
|
|
|
|
|
2017-11-15 00:23:33 +01:00
|
|
|
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
putsum(tp->data, tp->size, props->tucso, props->tucss, props->tucse);
|
2016-06-01 10:23:44 +02:00
|
|
|
}
|
2017-11-15 00:23:33 +01:00
|
|
|
if (tp->sum_needed & E1000_TXD_POPTS_IXSM) {
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
putsum(tp->data, tp->size, props->ipcso, props->ipcss, props->ipcse);
|
2016-06-01 10:23:44 +02:00
|
|
|
}
|
2008-11-21 17:25:17 +01:00
|
|
|
if (tp->vlan_needed) {
|
2009-11-19 19:44:55 +01:00
|
|
|
memmove(tp->vlan, tp->data, 4);
|
|
|
|
memmove(tp->data, tp->data + 4, 8);
|
2008-11-21 17:25:17 +01:00
|
|
|
memcpy(tp->data + 8, tp->vlan_header, 4);
|
2012-03-22 11:01:59 +01:00
|
|
|
e1000_send_packet(s, tp->vlan, tp->size + 4);
|
2015-11-11 14:52:39 +01:00
|
|
|
} else {
|
2012-03-22 11:01:59 +01:00
|
|
|
e1000_send_packet(s, tp->data, tp->size);
|
2015-11-11 14:52:39 +01:00
|
|
|
}
|
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, TPT);
|
|
|
|
e1000x_grow_8reg_if_not_full(s->mac_reg, TOTL, s->tx.size);
|
2015-11-11 14:52:43 +01:00
|
|
|
s->mac_reg[GPTC] = s->mac_reg[TPT];
|
2015-11-11 14:52:46 +01:00
|
|
|
s->mac_reg[GOTCL] = s->mac_reg[TOTL];
|
|
|
|
s->mac_reg[GOTCH] = s->mac_reg[TOTH];
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
|
|
|
|
{
|
2013-06-30 12:55:52 +02:00
|
|
|
PCIDevice *d = PCI_DEVICE(s);
|
2008-02-03 03:20:18 +01:00
|
|
|
uint32_t txd_lower = le32_to_cpu(dp->lower.data);
|
|
|
|
uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
|
2016-06-01 10:23:44 +02:00
|
|
|
unsigned int split_size = txd_lower & 0xffff, bytes, sz;
|
2013-06-04 10:49:48 +02:00
|
|
|
unsigned int msh = 0xfffff;
|
2008-02-03 03:20:18 +01:00
|
|
|
uint64_t addr;
|
|
|
|
struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
|
|
|
|
struct e1000_tx *tp = &s->tx;
|
|
|
|
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
|
2015-11-11 14:52:39 +01:00
|
|
|
if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (le32_to_cpu(xp->cmd_and_length) & E1000_TXD_CMD_TSE) {
|
|
|
|
e1000x_read_tx_ctx_descr(xp, &tp->tso_props);
|
2018-03-28 18:36:29 +02:00
|
|
|
s->use_tso_for_migration = 1;
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
tp->tso_frames = 0;
|
|
|
|
} else {
|
|
|
|
e1000x_read_tx_ctx_descr(xp, &tp->props);
|
2018-03-28 18:36:29 +02:00
|
|
|
s->use_tso_for_migration = 0;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
return;
|
2008-07-16 14:39:45 +02:00
|
|
|
} else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
|
|
|
|
// data descriptor
|
2011-03-07 21:04:07 +01:00
|
|
|
if (tp->size == 0) {
|
2017-11-15 00:23:33 +01:00
|
|
|
tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
|
2011-03-07 21:04:07 +01:00
|
|
|
}
|
2017-11-15 00:23:33 +01:00
|
|
|
tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
|
2010-11-11 16:10:04 +01:00
|
|
|
} else {
|
2008-07-16 14:39:45 +02:00
|
|
|
// legacy descriptor
|
2017-11-15 00:23:33 +01:00
|
|
|
tp->cptse = 0;
|
2010-11-11 16:10:04 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
if (e1000x_vlan_enabled(s->mac_reg) &&
|
|
|
|
e1000x_is_vlan_txd(txd_lower) &&
|
2017-11-15 00:23:33 +01:00
|
|
|
(tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
|
2008-11-21 17:25:17 +01:00
|
|
|
tp->vlan_needed = 1;
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(tp->vlan_header,
|
2015-03-13 06:21:59 +01:00
|
|
|
le16_to_cpu(s->mac_reg[VET]));
|
2013-11-05 17:38:34 +01:00
|
|
|
stw_be_p(tp->vlan_header + 2,
|
2008-11-21 17:25:17 +01:00
|
|
|
le16_to_cpu(dp->upper.fields.special));
|
|
|
|
}
|
2015-11-11 14:52:39 +01:00
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
addr = le64_to_cpu(dp->buffer_addr);
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (tp->cptse) {
|
|
|
|
msh = tp->tso_props.hdr_len + tp->tso_props.mss;
|
2008-07-16 14:39:45 +02:00
|
|
|
do {
|
|
|
|
bytes = split_size;
|
|
|
|
if (tp->size + bytes > msh)
|
|
|
|
bytes = msh - tp->size;
|
2012-01-23 14:30:43 +01:00
|
|
|
|
|
|
|
bytes = MIN(sizeof(tp->data) - tp->size, bytes);
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_read(d, addr, tp->data + tp->size, bytes);
|
2013-06-04 10:49:48 +02:00
|
|
|
sz = tp->size + bytes;
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (sz >= tp->tso_props.hdr_len
|
|
|
|
&& tp->size < tp->tso_props.hdr_len) {
|
|
|
|
memmove(tp->header, tp->data, tp->tso_props.hdr_len);
|
2013-06-04 10:49:48 +02:00
|
|
|
}
|
2008-07-16 14:39:45 +02:00
|
|
|
tp->size = sz;
|
|
|
|
addr += bytes;
|
|
|
|
if (sz == msh) {
|
|
|
|
xmit_seg(s);
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
memmove(tp->data, tp->header, tp->tso_props.hdr_len);
|
|
|
|
tp->size = tp->tso_props.hdr_len;
|
2008-07-16 14:39:45 +02:00
|
|
|
}
|
2015-09-04 18:21:06 +02:00
|
|
|
split_size -= bytes;
|
|
|
|
} while (bytes && split_size);
|
2008-07-16 14:39:45 +02:00
|
|
|
} else {
|
2012-01-23 14:30:43 +01:00
|
|
|
split_size = MIN(sizeof(tp->data) - tp->size, split_size);
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_read(d, addr, tp->data + tp->size, split_size);
|
2008-07-16 14:39:45 +02:00
|
|
|
tp->size += split_size;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!(txd_lower & E1000_TXD_CMD_EOP))
|
|
|
|
return;
|
e1000: Separate TSO and non-TSO contexts, fixing UDP TX corruption
The device is supposed to maintain two distinct contexts for transmit
offloads: one has parameters for both segmentation and checksum
offload, the other only for checksum offload. The guest driver can
send two context descriptors, one for each context (the TSE flag
specifies which). Then the guest can refer to one or the other context
in subsequent transmit data descriptors, depending on what offloads it
wants applied to each packet.
Currently the e1000 device stores just one context, and misinterprets
the TSE flags in the context and data descriptors. This is often okay:
Linux happens to send a fresh context descriptor before every data
descriptor, so forgetting the other context doesn't matter. Windows
does rely on separate contexts for TSO vs. non-TSO packets, but for
mostly-TCP traffic the two contexts have identical TCP-specific
offload parameters so confusing them doesn't matter.
One case where this confusion matters is when a Windows guest sets up
a TSO context for TCP and a non-TSO context for UDP, and then
transmits both TCP and UDP traffic in parallel. The e1000 device
sometimes ends up using TCP-specific parameters while doing checksum
offload on a UDP datagram: it writes the checksum to offset 16 (the
correct location for a TCP checksum), stomping on two bytes of UDP
data, and leaving the wrong value in the actual UDP checksum field at
offset 6. (Even worse, the host network stack may then recompute the
UDP checksum, "correcting" it to match the corrupt data before sending
it out a physical interface.)
Correct this by tracking the TSO context independently of the non-TSO
context, and selecting the appropriate context based on the TSE flag
in each transmit data descriptor.
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-11-15 00:23:34 +01:00
|
|
|
if (!(tp->cptse && tp->size < tp->tso_props.hdr_len)) {
|
2008-02-03 03:20:18 +01:00
|
|
|
xmit_seg(s);
|
2013-06-04 10:49:48 +02:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
tp->tso_frames = 0;
|
2017-11-15 00:23:33 +01:00
|
|
|
tp->sum_needed = 0;
|
2008-11-21 17:25:17 +01:00
|
|
|
tp->vlan_needed = 0;
|
2008-02-03 03:20:18 +01:00
|
|
|
tp->size = 0;
|
2017-11-15 00:23:33 +01:00
|
|
|
tp->cptse = 0;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
2011-10-31 07:06:52 +01:00
|
|
|
txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2013-06-30 12:55:52 +02:00
|
|
|
PCIDevice *d = PCI_DEVICE(s);
|
2008-02-03 03:20:18 +01:00
|
|
|
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
|
|
|
|
|
|
|
|
if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
|
|
|
|
return 0;
|
|
|
|
txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
|
|
|
|
~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
|
|
|
|
dp->upper.data = cpu_to_le32(txd_upper);
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp),
|
2011-11-04 02:03:33 +01:00
|
|
|
&dp->upper, sizeof(dp->upper));
|
2008-02-03 03:20:18 +01:00
|
|
|
return E1000_ICR_TXDW;
|
|
|
|
}
|
|
|
|
|
2011-03-26 19:37:56 +01:00
|
|
|
static uint64_t tx_desc_base(E1000State *s)
|
|
|
|
{
|
|
|
|
uint64_t bah = s->mac_reg[TDBAH];
|
|
|
|
uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
|
|
|
|
|
|
|
|
return (bah << 32) + bal;
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static void
|
|
|
|
start_xmit(E1000State *s)
|
|
|
|
{
|
2013-06-30 12:55:52 +02:00
|
|
|
PCIDevice *d = PCI_DEVICE(s);
|
2011-10-31 07:06:52 +01:00
|
|
|
dma_addr_t base;
|
2008-02-03 03:20:18 +01:00
|
|
|
struct e1000_tx_desc desc;
|
|
|
|
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
|
|
|
|
|
|
|
|
if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
|
|
|
|
DBGOUT(TX, "tx disabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
|
2011-03-26 19:37:56 +01:00
|
|
|
base = tx_desc_base(s) +
|
2008-02-03 03:20:18 +01:00
|
|
|
sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_read(d, base, &desc, sizeof(desc));
|
2008-02-03 03:20:18 +01:00
|
|
|
|
|
|
|
DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
|
2008-05-13 16:35:34 +02:00
|
|
|
(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
|
2008-02-03 03:20:18 +01:00
|
|
|
desc.upper.data);
|
|
|
|
|
|
|
|
process_tx_desc(s, &desc);
|
2011-10-31 07:06:52 +01:00
|
|
|
cause |= txdesc_writeback(s, base, &desc);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
|
|
|
if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
|
|
|
|
s->mac_reg[TDH] = 0;
|
|
|
|
/*
|
|
|
|
* the following could happen only if guest sw assigns
|
|
|
|
* bogus values to TDT/TDLEN.
|
|
|
|
* there's nothing too intelligent we could do about this.
|
|
|
|
*/
|
e1000: eliminate infinite loops on out-of-bounds transfer start
The start_xmit() and e1000_receive_iov() functions implement DMA transfers
iterating over a set of descriptors that the guest's e1000 driver
prepares:
- the TDLEN and RDLEN registers store the total size of the descriptor
area,
- while the TDH and RDH registers store the offset (in whole tx / rx
descriptors) into the area where the transfer is supposed to start.
Each time a descriptor is processed, the TDH and RDH register is bumped
(as appropriate for the transfer direction).
QEMU already contains logic to deal with bogus transfers submitted by the
guest:
- Normally, the transmit case wants to increase TDH from its initial value
to TDT. (TDT is allowed to be numerically smaller than the initial TDH
value; wrapping at or above TDLEN bytes to zero is normal.) The failsafe
that QEMU currently has here is a check against reaching the original
TDH value again -- a complete wraparound, which should never happen.
- In the receive case RDH is increased from its initial value until
"total_size" bytes have been received; preferably in a single step, or
in "s->rxbuf_size" byte steps, if the latter is smaller. However, null
RX descriptors are skipped without receiving data, while RDH is
incremented just the same. QEMU tries to prevent an infinite loop
(processing only null RX descriptors) by detecting whether RDH assumes
its original value during the loop. (Again, wrapping from RDLEN to 0 is
normal.)
What both directions miss is that the guest could program TDLEN and RDLEN
so low, and the initial TDH and RDH so high, that these registers will
immediately be truncated to zero, and then never reassume their initial
values in the loop -- a full wraparound will never occur.
The condition that expresses this is:
xdh_start >= s->mac_reg[XDLEN] / sizeof(desc)
i.e., TDH or RDH start out after the last whole rx or tx descriptor that
fits into the TDLEN or RDLEN sized area.
This condition could be checked before we enter the loops, but
pci_dma_read() / pci_dma_write() knows how to fill in buffers safely for
bogus DMA addresses, so we just extend the existing failsafes with the
above condition.
This is CVE-2016-1981.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Petr Matousek <pmatouse@redhat.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Prasad Pandit <ppandit@redhat.com>
Cc: Michael Roth <mdroth@linux.vnet.ibm.com>
Cc: Jason Wang <jasowang@redhat.com>
Cc: qemu-stable@nongnu.org
RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1296044
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-01-19 14:17:20 +01:00
|
|
|
if (s->mac_reg[TDH] == tdh_start ||
|
|
|
|
tdh_start >= s->mac_reg[TDLEN] / sizeof(desc)) {
|
2008-02-03 03:20:18 +01:00
|
|
|
DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
|
|
|
|
tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
set_ics(s, 0, cause);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
receive_filter(E1000State *s, const uint8_t *buf, int size)
|
|
|
|
{
|
2016-06-01 10:23:44 +02:00
|
|
|
uint32_t rctl = s->mac_reg[RCTL];
|
2015-11-11 14:52:45 +01:00
|
|
|
int isbcast = !memcmp(buf, bcast, sizeof bcast), ismcast = (buf[0] & 1);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
if (e1000x_is_vlan_packet(buf, le16_to_cpu(s->mac_reg[VET])) &&
|
|
|
|
e1000x_vlan_rx_filter_enabled(s->mac_reg)) {
|
2016-06-16 19:17:26 +02:00
|
|
|
uint16_t vid = lduw_be_p(buf + 14);
|
|
|
|
uint32_t vfta = ldl_le_p((uint32_t*)(s->mac_reg + VFTA) +
|
|
|
|
((vid >> 5) & 0x7f));
|
2008-11-21 17:25:17 +01:00
|
|
|
if ((vfta & (1 << (vid & 0x1f))) == 0)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-11 14:52:45 +01:00
|
|
|
if (!isbcast && !ismcast && (rctl & E1000_RCTL_UPE)) { /* promiscuous ucast */
|
2008-02-03 03:20:18 +01:00
|
|
|
return 1;
|
2015-11-11 14:52:45 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2015-11-11 14:52:45 +01:00
|
|
|
if (ismcast && (rctl & E1000_RCTL_MPE)) { /* promiscuous mcast */
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, MPRC);
|
2008-02-03 03:20:18 +01:00
|
|
|
return 1;
|
2015-11-11 14:52:45 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2015-11-11 14:52:45 +01:00
|
|
|
if (isbcast && (rctl & E1000_RCTL_BAM)) { /* broadcast enabled */
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, BPRC);
|
2008-02-03 03:20:18 +01:00
|
|
|
return 1;
|
2015-11-11 14:52:46 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
return e1000x_rx_group_filter(s->mac_reg, buf);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2009-01-08 20:45:50 +01:00
|
|
|
static void
|
2012-07-24 17:35:13 +02:00
|
|
|
e1000_set_link_status(NetClientState *nc)
|
2009-01-08 20:45:50 +01:00
|
|
|
{
|
2013-01-30 12:12:23 +01:00
|
|
|
E1000State *s = qemu_get_nic_opaque(nc);
|
2009-01-08 20:45:50 +01:00
|
|
|
uint32_t old_status = s->mac_reg[STATUS];
|
|
|
|
|
2011-08-17 11:03:14 +02:00
|
|
|
if (nc->link_down) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg);
|
2011-08-17 11:03:14 +02:00
|
|
|
} else {
|
2014-06-19 21:40:51 +02:00
|
|
|
if (have_autoneg(s) &&
|
2014-06-19 17:55:33 +02:00
|
|
|
!(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer);
|
2014-06-19 17:55:33 +02:00
|
|
|
} else {
|
|
|
|
e1000_link_up(s);
|
|
|
|
}
|
2011-08-17 11:03:14 +02:00
|
|
|
}
|
2009-01-08 20:45:50 +01:00
|
|
|
|
|
|
|
if (s->mac_reg[STATUS] != old_status)
|
|
|
|
set_ics(s, 0, E1000_ICR_LSC);
|
|
|
|
}
|
|
|
|
|
2011-02-15 17:27:55 +01:00
|
|
|
static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
|
|
|
|
{
|
|
|
|
int bufs;
|
|
|
|
/* Fast-path short packets */
|
|
|
|
if (total_size <= s->rxbuf_size) {
|
2012-10-19 07:56:55 +02:00
|
|
|
return s->mac_reg[RDH] != s->mac_reg[RDT];
|
2011-02-15 17:27:55 +01:00
|
|
|
}
|
|
|
|
if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
|
|
|
|
bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
|
2012-10-19 07:56:55 +02:00
|
|
|
} else if (s->mac_reg[RDH] > s->mac_reg[RDT]) {
|
2011-02-15 17:27:55 +01:00
|
|
|
bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
|
|
|
|
s->mac_reg[RDT] - s->mac_reg[RDH];
|
|
|
|
} else {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return total_size <= bufs * s->rxbuf_size;
|
|
|
|
}
|
|
|
|
|
2011-03-27 13:37:35 +02:00
|
|
|
static int
|
2012-07-24 17:35:13 +02:00
|
|
|
e1000_can_receive(NetClientState *nc)
|
2011-03-27 13:37:35 +02:00
|
|
|
{
|
2013-01-30 12:12:23 +01:00
|
|
|
E1000State *s = qemu_get_nic_opaque(nc);
|
2011-03-27 13:37:35 +02:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
return e1000x_rx_ready(&s->parent_obj, s->mac_reg) &&
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
e1000_has_rxbufs(s, 1) && !timer_pending(s->flush_queue_timer);
|
2011-03-27 13:37:35 +02:00
|
|
|
}
|
|
|
|
|
2011-03-26 19:37:56 +01:00
|
|
|
static uint64_t rx_desc_base(E1000State *s)
|
|
|
|
{
|
|
|
|
uint64_t bah = s->mac_reg[RDBAH];
|
|
|
|
uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
|
|
|
|
|
|
|
|
return (bah << 32) + bal;
|
|
|
|
}
|
|
|
|
|
2018-10-16 11:40:45 +02:00
|
|
|
static void
|
|
|
|
e1000_receiver_overrun(E1000State *s, size_t size)
|
|
|
|
{
|
|
|
|
trace_e1000_receiver_overrun(size, s->mac_reg[RDH], s->mac_reg[RDT]);
|
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, RNBC);
|
|
|
|
e1000x_inc_reg_if_not_full(s->mac_reg, MPC);
|
|
|
|
set_ics(s, 0, E1000_ICS_RXO);
|
|
|
|
}
|
|
|
|
|
2009-05-18 14:40:55 +02:00
|
|
|
static ssize_t
|
2013-09-12 10:47:37 +02:00
|
|
|
e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2013-01-30 12:12:23 +01:00
|
|
|
E1000State *s = qemu_get_nic_opaque(nc);
|
2013-06-30 12:55:52 +02:00
|
|
|
PCIDevice *d = PCI_DEVICE(s);
|
2008-02-03 03:20:18 +01:00
|
|
|
struct e1000_rx_desc desc;
|
2011-10-31 07:06:52 +01:00
|
|
|
dma_addr_t base;
|
2008-02-03 03:20:18 +01:00
|
|
|
unsigned int n, rdt;
|
|
|
|
uint32_t rdh_start;
|
2008-11-21 17:25:17 +01:00
|
|
|
uint16_t vlan_special = 0;
|
2013-09-12 10:47:37 +02:00
|
|
|
uint8_t vlan_status = 0;
|
2010-09-18 22:43:45 +02:00
|
|
|
uint8_t min_buf[MIN_BUF_SIZE];
|
2013-09-12 10:47:37 +02:00
|
|
|
struct iovec min_iov;
|
|
|
|
uint8_t *filter_buf = iov->iov_base;
|
|
|
|
size_t size = iov_size(iov, iovcnt);
|
|
|
|
size_t iov_ofs = 0;
|
2011-02-15 17:27:48 +01:00
|
|
|
size_t desc_offset;
|
|
|
|
size_t desc_size;
|
|
|
|
size_t total_size;
|
2013-02-05 20:00:21 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
if (!e1000x_hw_rx_enabled(s->mac_reg)) {
|
2009-05-18 14:40:55 +02:00
|
|
|
return -1;
|
2013-02-05 20:00:21 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
if (timer_pending(s->flush_queue_timer)) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-18 22:43:45 +02:00
|
|
|
/* Pad to minimum Ethernet frame length */
|
|
|
|
if (size < sizeof(min_buf)) {
|
2013-09-12 10:47:37 +02:00
|
|
|
iov_to_buf(iov, iovcnt, 0, min_buf, size);
|
2010-09-18 22:43:45 +02:00
|
|
|
memset(&min_buf[size], 0, sizeof(min_buf) - size);
|
2013-09-12 10:47:37 +02:00
|
|
|
min_iov.iov_base = filter_buf = min_buf;
|
|
|
|
min_iov.iov_len = size = sizeof(min_buf);
|
|
|
|
iovcnt = 1;
|
|
|
|
iov = &min_iov;
|
|
|
|
} else if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) {
|
|
|
|
/* This is very unlikely, but may happen. */
|
|
|
|
iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN);
|
|
|
|
filter_buf = min_buf;
|
2010-09-18 22:43:45 +02:00
|
|
|
}
|
|
|
|
|
2012-12-03 05:11:22 +01:00
|
|
|
/* Discard oversized packets if !LPE and !SBP. */
|
2016-06-01 10:23:44 +02:00
|
|
|
if (e1000x_is_oversized(s->mac_reg, size)) {
|
2012-12-03 05:11:22 +01:00
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2013-09-12 10:47:37 +02:00
|
|
|
if (!receive_filter(s, filter_buf, size)) {
|
2009-05-18 14:40:55 +02:00
|
|
|
return size;
|
2013-09-12 10:47:37 +02:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
if (e1000x_vlan_enabled(s->mac_reg) &&
|
|
|
|
e1000x_is_vlan_packet(filter_buf, le16_to_cpu(s->mac_reg[VET]))) {
|
2016-06-16 19:17:26 +02:00
|
|
|
vlan_special = cpu_to_le16(lduw_be_p(filter_buf + 14));
|
2013-09-12 10:47:37 +02:00
|
|
|
iov_ofs = 4;
|
|
|
|
if (filter_buf == iov->iov_base) {
|
|
|
|
memmove(filter_buf + 4, filter_buf, 12);
|
|
|
|
} else {
|
|
|
|
iov_from_buf(iov, iovcnt, 4, filter_buf, 12);
|
|
|
|
while (iov->iov_len <= iov_ofs) {
|
|
|
|
iov_ofs -= iov->iov_len;
|
|
|
|
iov++;
|
|
|
|
}
|
|
|
|
}
|
2008-11-21 17:25:17 +01:00
|
|
|
vlan_status = E1000_RXD_STAT_VP;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
rdh_start = s->mac_reg[RDH];
|
2011-02-15 17:27:48 +01:00
|
|
|
desc_offset = 0;
|
2016-06-01 10:23:44 +02:00
|
|
|
total_size = size + e1000x_fcs_len(s->mac_reg);
|
2011-02-15 17:27:55 +01:00
|
|
|
if (!e1000_has_rxbufs(s, total_size)) {
|
2018-10-16 11:40:45 +02:00
|
|
|
e1000_receiver_overrun(s, total_size);
|
|
|
|
return -1;
|
2011-02-15 17:27:55 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
do {
|
2011-02-15 17:27:48 +01:00
|
|
|
desc_size = total_size - desc_offset;
|
|
|
|
if (desc_size > s->rxbuf_size) {
|
|
|
|
desc_size = s->rxbuf_size;
|
|
|
|
}
|
2011-03-26 19:37:56 +01:00
|
|
|
base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_read(d, base, &desc, sizeof(desc));
|
2008-11-21 17:25:17 +01:00
|
|
|
desc.special = vlan_special;
|
|
|
|
desc.status |= (vlan_status | E1000_RXD_STAT_DD);
|
2008-02-03 03:20:18 +01:00
|
|
|
if (desc.buffer_addr) {
|
2011-02-15 17:27:48 +01:00
|
|
|
if (desc_offset < size) {
|
2013-09-12 10:47:37 +02:00
|
|
|
size_t iov_copy;
|
|
|
|
hwaddr ba = le64_to_cpu(desc.buffer_addr);
|
2011-02-15 17:27:48 +01:00
|
|
|
size_t copy_size = size - desc_offset;
|
|
|
|
if (copy_size > s->rxbuf_size) {
|
|
|
|
copy_size = s->rxbuf_size;
|
|
|
|
}
|
2013-09-12 10:47:37 +02:00
|
|
|
do {
|
|
|
|
iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
|
|
|
|
pci_dma_write(d, ba, iov->iov_base + iov_ofs, iov_copy);
|
|
|
|
copy_size -= iov_copy;
|
|
|
|
ba += iov_copy;
|
|
|
|
iov_ofs += iov_copy;
|
|
|
|
if (iov_ofs == iov->iov_len) {
|
|
|
|
iov++;
|
|
|
|
iov_ofs = 0;
|
|
|
|
}
|
|
|
|
} while (copy_size);
|
2011-02-15 17:27:48 +01:00
|
|
|
}
|
|
|
|
desc_offset += desc_size;
|
2011-02-15 17:27:52 +01:00
|
|
|
desc.length = cpu_to_le16(desc_size);
|
2011-02-15 17:27:48 +01:00
|
|
|
if (desc_offset >= total_size) {
|
|
|
|
desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
|
|
|
|
} else {
|
2011-02-15 17:27:52 +01:00
|
|
|
/* Guest zeroing out status is not a hardware requirement.
|
|
|
|
Clear EOP in case guest didn't do it. */
|
|
|
|
desc.status &= ~E1000_RXD_STAT_EOP;
|
2011-02-15 17:27:48 +01:00
|
|
|
}
|
2010-11-11 16:10:04 +01:00
|
|
|
} else { // as per intel docs; skip descriptors with null buf addr
|
2008-02-03 03:20:18 +01:00
|
|
|
DBGOUT(RX, "Null RX descriptor!!\n");
|
2010-11-11 16:10:04 +01:00
|
|
|
}
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_dma_write(d, base, &desc, sizeof(desc));
|
2008-02-03 03:20:18 +01:00
|
|
|
|
|
|
|
if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
|
|
|
|
s->mac_reg[RDH] = 0;
|
|
|
|
/* see comment in start_xmit; same here */
|
e1000: eliminate infinite loops on out-of-bounds transfer start
The start_xmit() and e1000_receive_iov() functions implement DMA transfers
iterating over a set of descriptors that the guest's e1000 driver
prepares:
- the TDLEN and RDLEN registers store the total size of the descriptor
area,
- while the TDH and RDH registers store the offset (in whole tx / rx
descriptors) into the area where the transfer is supposed to start.
Each time a descriptor is processed, the TDH and RDH register is bumped
(as appropriate for the transfer direction).
QEMU already contains logic to deal with bogus transfers submitted by the
guest:
- Normally, the transmit case wants to increase TDH from its initial value
to TDT. (TDT is allowed to be numerically smaller than the initial TDH
value; wrapping at or above TDLEN bytes to zero is normal.) The failsafe
that QEMU currently has here is a check against reaching the original
TDH value again -- a complete wraparound, which should never happen.
- In the receive case RDH is increased from its initial value until
"total_size" bytes have been received; preferably in a single step, or
in "s->rxbuf_size" byte steps, if the latter is smaller. However, null
RX descriptors are skipped without receiving data, while RDH is
incremented just the same. QEMU tries to prevent an infinite loop
(processing only null RX descriptors) by detecting whether RDH assumes
its original value during the loop. (Again, wrapping from RDLEN to 0 is
normal.)
What both directions miss is that the guest could program TDLEN and RDLEN
so low, and the initial TDH and RDH so high, that these registers will
immediately be truncated to zero, and then never reassume their initial
values in the loop -- a full wraparound will never occur.
The condition that expresses this is:
xdh_start >= s->mac_reg[XDLEN] / sizeof(desc)
i.e., TDH or RDH start out after the last whole rx or tx descriptor that
fits into the TDLEN or RDLEN sized area.
This condition could be checked before we enter the loops, but
pci_dma_read() / pci_dma_write() knows how to fill in buffers safely for
bogus DMA addresses, so we just extend the existing failsafes with the
above condition.
This is CVE-2016-1981.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Petr Matousek <pmatouse@redhat.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Prasad Pandit <ppandit@redhat.com>
Cc: Michael Roth <mdroth@linux.vnet.ibm.com>
Cc: Jason Wang <jasowang@redhat.com>
Cc: qemu-stable@nongnu.org
RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1296044
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-01-19 14:17:20 +01:00
|
|
|
if (s->mac_reg[RDH] == rdh_start ||
|
|
|
|
rdh_start >= s->mac_reg[RDLEN] / sizeof(desc)) {
|
2008-02-03 03:20:18 +01:00
|
|
|
DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
|
|
|
|
rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
|
2018-10-16 11:40:45 +02:00
|
|
|
e1000_receiver_overrun(s, total_size);
|
2009-05-18 14:40:55 +02:00
|
|
|
return -1;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
2011-02-15 17:27:48 +01:00
|
|
|
} while (desc_offset < total_size);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2016-06-01 10:23:44 +02:00
|
|
|
e1000x_update_rx_total_stats(s->mac_reg, size, total_size);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
|
|
|
n = E1000_ICS_RXT0;
|
|
|
|
if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
|
|
|
|
rdt += s->mac_reg[RDLEN] / sizeof(desc);
|
2009-03-20 17:13:47 +01:00
|
|
|
if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
|
|
|
|
s->rxbuf_min_shift)
|
2008-02-03 03:20:18 +01:00
|
|
|
n |= E1000_ICS_RXDMT0;
|
|
|
|
|
|
|
|
set_ics(s, 0, n);
|
2009-05-18 14:40:55 +02:00
|
|
|
|
|
|
|
return size;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2013-09-12 10:47:37 +02:00
|
|
|
static ssize_t
|
|
|
|
e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
|
|
|
{
|
|
|
|
const struct iovec iov = {
|
|
|
|
.iov_base = (uint8_t *)buf,
|
|
|
|
.iov_len = size
|
|
|
|
};
|
|
|
|
|
|
|
|
return e1000_receive_iov(nc, &iov, 1);
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static uint32_t
|
|
|
|
mac_readreg(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
return s->mac_reg[index];
|
|
|
|
}
|
|
|
|
|
2015-11-11 14:52:42 +01:00
|
|
|
static uint32_t
|
|
|
|
mac_low4_read(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
return s->mac_reg[index] & 0xf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
mac_low11_read(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
return s->mac_reg[index] & 0x7ff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
mac_low13_read(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
return s->mac_reg[index] & 0x1fff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
mac_low16_read(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
return s->mac_reg[index] & 0xffff;
|
|
|
|
}
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static uint32_t
|
|
|
|
mac_icr_read(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
uint32_t ret = s->mac_reg[ICR];
|
|
|
|
|
|
|
|
DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
|
|
|
|
set_interrupt_cause(s, 0, 0);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
mac_read_clr4(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
uint32_t ret = s->mac_reg[index];
|
|
|
|
|
|
|
|
s->mac_reg[index] = 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
mac_read_clr8(E1000State *s, int index)
|
|
|
|
{
|
|
|
|
uint32_t ret = s->mac_reg[index];
|
|
|
|
|
|
|
|
s->mac_reg[index] = 0;
|
|
|
|
s->mac_reg[index-1] = 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mac_writereg(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
2013-10-17 09:02:49 +02:00
|
|
|
uint32_t macaddr[2];
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
s->mac_reg[index] = val;
|
2013-10-17 09:02:49 +02:00
|
|
|
|
2013-11-18 20:41:44 +01:00
|
|
|
if (index == RA + 1) {
|
2013-10-17 09:02:49 +02:00
|
|
|
macaddr[0] = cpu_to_le32(s->mac_reg[RA]);
|
|
|
|
macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]);
|
|
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), (uint8_t *)macaddr);
|
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_rdt(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[index] = val & 0xffff;
|
2012-08-09 16:45:56 +02:00
|
|
|
if (e1000_has_rxbufs(s, 1)) {
|
2013-01-30 12:12:22 +01:00
|
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
2012-08-09 16:45:56 +02:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_16bit(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[index] = val & 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_dlen(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[index] = val & 0xfff80;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_tctl(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[index] = val;
|
|
|
|
s->mac_reg[TDT] &= 0xffff;
|
|
|
|
start_xmit(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_icr(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
DBGOUT(INTERRUPT, "set_icr %x\n", val);
|
|
|
|
set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_imc(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[IMS] &= ~val;
|
|
|
|
set_ics(s, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
set_ims(E1000State *s, int index, uint32_t val)
|
|
|
|
{
|
|
|
|
s->mac_reg[IMS] |= val;
|
|
|
|
set_ics(s, 0, 0);
|
|
|
|
}
|
|
|
|
|
2015-11-11 14:52:39 +01:00
|
|
|
#define getreg(x) [x] = mac_readreg
|
2008-02-03 03:20:18 +01:00
|
|
|
static uint32_t (*macreg_readops[])(E1000State *, int) = {
|
2015-11-11 14:52:39 +01:00
|
|
|
getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
|
|
|
|
getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
|
|
|
|
getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
|
|
|
|
getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
|
|
|
|
getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
|
|
|
|
getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
|
|
|
|
getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
|
2015-11-11 14:52:42 +01:00
|
|
|
getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
|
|
|
|
getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
|
|
|
|
getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
|
2017-09-03 18:37:26 +02:00
|
|
|
getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
|
2015-11-11 14:52:42 +01:00
|
|
|
getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
|
|
|
|
getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
|
2015-11-11 14:52:46 +01:00
|
|
|
getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL),
|
|
|
|
getreg(GOTCL),
|
2015-11-11 14:52:39 +01:00
|
|
|
|
|
|
|
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
|
2015-11-11 14:52:46 +01:00
|
|
|
[GOTCH] = mac_read_clr8, [GORCH] = mac_read_clr8,
|
|
|
|
[PRC64] = mac_read_clr4, [PRC127] = mac_read_clr4,
|
|
|
|
[PRC255] = mac_read_clr4, [PRC511] = mac_read_clr4,
|
|
|
|
[PRC1023] = mac_read_clr4, [PRC1522] = mac_read_clr4,
|
|
|
|
[PTC64] = mac_read_clr4, [PTC127] = mac_read_clr4,
|
|
|
|
[PTC255] = mac_read_clr4, [PTC511] = mac_read_clr4,
|
|
|
|
[PTC1023] = mac_read_clr4, [PTC1522] = mac_read_clr4,
|
2015-11-11 14:52:39 +01:00
|
|
|
[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
|
|
|
|
[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
|
2015-11-11 14:52:46 +01:00
|
|
|
[RUC] = mac_read_clr4, [ROC] = mac_read_clr4,
|
|
|
|
[BPRC] = mac_read_clr4, [MPRC] = mac_read_clr4,
|
|
|
|
[TSCTC] = mac_read_clr4, [BPTC] = mac_read_clr4,
|
|
|
|
[MPTC] = mac_read_clr4,
|
2015-11-11 14:52:39 +01:00
|
|
|
[ICR] = mac_icr_read, [EECD] = get_eecd,
|
|
|
|
[EERD] = flash_eerd_read,
|
2015-11-11 14:52:42 +01:00
|
|
|
[RDFH] = mac_low13_read, [RDFT] = mac_low13_read,
|
|
|
|
[RDFHS] = mac_low13_read, [RDFTS] = mac_low13_read,
|
|
|
|
[RDFPC] = mac_low13_read,
|
|
|
|
[TDFH] = mac_low11_read, [TDFT] = mac_low11_read,
|
|
|
|
[TDFHS] = mac_low13_read, [TDFTS] = mac_low13_read,
|
|
|
|
[TDFPC] = mac_low13_read,
|
|
|
|
[AIT] = mac_low16_read,
|
2015-11-11 14:52:39 +01:00
|
|
|
|
|
|
|
[CRCERRS ... MPC] = &mac_readreg,
|
2015-11-11 14:52:42 +01:00
|
|
|
[IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg,
|
|
|
|
[FFLT ... FFLT+6] = &mac_low11_read,
|
2015-11-11 14:52:39 +01:00
|
|
|
[RA ... RA+31] = &mac_readreg,
|
2015-11-11 14:52:42 +01:00
|
|
|
[WUPM ... WUPM+31] = &mac_readreg,
|
2015-11-11 14:52:39 +01:00
|
|
|
[MTA ... MTA+127] = &mac_readreg,
|
2008-11-21 17:25:17 +01:00
|
|
|
[VFTA ... VFTA+127] = &mac_readreg,
|
2015-11-11 14:52:42 +01:00
|
|
|
[FFMT ... FFMT+254] = &mac_low4_read,
|
|
|
|
[FFVT ... FFVT+254] = &mac_readreg,
|
|
|
|
[PBM ... PBM+16383] = &mac_readreg,
|
2008-02-03 03:20:18 +01:00
|
|
|
};
|
2008-12-22 21:33:55 +01:00
|
|
|
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2015-11-11 14:52:39 +01:00
|
|
|
#define putreg(x) [x] = mac_writereg
|
2008-02-03 03:20:18 +01:00
|
|
|
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
|
2015-11-11 14:52:39 +01:00
|
|
|
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
|
|
|
|
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
|
2015-11-11 14:52:42 +01:00
|
|
|
putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
|
|
|
|
putreg(TDFH), putreg(TDFT), putreg(TDFHS), putreg(TDFTS),
|
|
|
|
putreg(TDFPC), putreg(RDFH), putreg(RDFT), putreg(RDFHS),
|
|
|
|
putreg(RDFTS), putreg(RDFPC), putreg(IPAV), putreg(WUC),
|
|
|
|
putreg(WUS), putreg(AIT),
|
2015-11-11 14:52:39 +01:00
|
|
|
|
|
|
|
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
|
|
|
|
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
|
|
|
|
[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
|
|
|
|
[IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
|
|
|
|
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
|
|
|
|
[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
|
|
|
|
[ITR] = set_16bit,
|
|
|
|
|
2015-11-11 14:52:42 +01:00
|
|
|
[IP6AT ... IP6AT+3] = &mac_writereg, [IP4AT ... IP4AT+6] = &mac_writereg,
|
|
|
|
[FFLT ... FFLT+6] = &mac_writereg,
|
2015-11-11 14:52:39 +01:00
|
|
|
[RA ... RA+31] = &mac_writereg,
|
2015-11-11 14:52:42 +01:00
|
|
|
[WUPM ... WUPM+31] = &mac_writereg,
|
2015-11-11 14:52:39 +01:00
|
|
|
[MTA ... MTA+127] = &mac_writereg,
|
2008-11-21 17:25:17 +01:00
|
|
|
[VFTA ... VFTA+127] = &mac_writereg,
|
2015-11-11 14:52:42 +01:00
|
|
|
[FFMT ... FFMT+254] = &mac_writereg, [FFVT ... FFVT+254] = &mac_writereg,
|
|
|
|
[PBM ... PBM+16383] = &mac_writereg,
|
2008-02-03 03:20:18 +01:00
|
|
|
};
|
2012-03-22 11:02:24 +01:00
|
|
|
|
2008-12-22 21:33:55 +01:00
|
|
|
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
|
2008-02-03 03:20:18 +01:00
|
|
|
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 };
|
|
|
|
|
|
|
|
#define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED)
|
|
|
|
/* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p]
|
|
|
|
* f - flag bits (up to 6 possible flags)
|
|
|
|
* n - flag needed
|
|
|
|
* p - partially implenented */
|
|
|
|
static const uint8_t mac_reg_access[0x8000] = {
|
|
|
|
[RDTR] = markflag(MIT), [TADV] = markflag(MIT),
|
|
|
|
[RADV] = markflag(MIT), [ITR] = markflag(MIT),
|
2015-11-11 14:52:42 +01:00
|
|
|
|
|
|
|
[IPAV] = markflag(MAC), [WUC] = markflag(MAC),
|
|
|
|
[IP6AT] = markflag(MAC), [IP4AT] = markflag(MAC),
|
|
|
|
[FFVT] = markflag(MAC), [WUPM] = markflag(MAC),
|
|
|
|
[ECOL] = markflag(MAC), [MCC] = markflag(MAC),
|
|
|
|
[DC] = markflag(MAC), [TNCRS] = markflag(MAC),
|
|
|
|
[RLEC] = markflag(MAC), [XONRXC] = markflag(MAC),
|
|
|
|
[XOFFTXC] = markflag(MAC), [RFC] = markflag(MAC),
|
|
|
|
[TSCTFC] = markflag(MAC), [MGTPRC] = markflag(MAC),
|
|
|
|
[WUS] = markflag(MAC), [AIT] = markflag(MAC),
|
|
|
|
[FFLT] = markflag(MAC), [FFMT] = markflag(MAC),
|
|
|
|
[SCC] = markflag(MAC), [FCRUC] = markflag(MAC),
|
|
|
|
[LATECOL] = markflag(MAC), [COLC] = markflag(MAC),
|
2017-09-03 18:37:26 +02:00
|
|
|
[SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC),
|
2015-11-11 14:52:42 +01:00
|
|
|
[XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC),
|
|
|
|
[RJC] = markflag(MAC), [RNBC] = markflag(MAC),
|
|
|
|
[MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC),
|
2015-11-11 14:52:46 +01:00
|
|
|
[RUC] = markflag(MAC), [ROC] = markflag(MAC),
|
|
|
|
[GORCL] = markflag(MAC), [GORCH] = markflag(MAC),
|
|
|
|
[GOTCL] = markflag(MAC), [GOTCH] = markflag(MAC),
|
|
|
|
[BPRC] = markflag(MAC), [MPRC] = markflag(MAC),
|
|
|
|
[TSCTC] = markflag(MAC), [PRC64] = markflag(MAC),
|
|
|
|
[PRC127] = markflag(MAC), [PRC255] = markflag(MAC),
|
|
|
|
[PRC511] = markflag(MAC), [PRC1023] = markflag(MAC),
|
|
|
|
[PRC1522] = markflag(MAC), [PTC64] = markflag(MAC),
|
|
|
|
[PTC127] = markflag(MAC), [PTC255] = markflag(MAC),
|
|
|
|
[PTC511] = markflag(MAC), [PTC1023] = markflag(MAC),
|
|
|
|
[PTC1522] = markflag(MAC), [MPTC] = markflag(MAC),
|
|
|
|
[BPTC] = markflag(MAC),
|
2015-11-11 14:52:42 +01:00
|
|
|
|
|
|
|
[TDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[TDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[TDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[TDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[TDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[RDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[RDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[RDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[RDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[RDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
|
|
|
[PBM] = markflag(MAC) | MAC_ACCESS_PARTIAL,
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
};
|
|
|
|
|
2008-02-03 03:20:18 +01:00
|
|
|
static void
|
2012-10-23 12:30:10 +02:00
|
|
|
e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
|
2011-08-08 15:09:08 +02:00
|
|
|
unsigned size)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
2008-12-01 19:59:50 +01:00
|
|
|
unsigned int index = (addr & 0x1ffff) >> 2;
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2010-11-11 16:10:04 +01:00
|
|
|
if (index < NWRITEOPS && macreg_writeops[index]) {
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
|
|
|
|
|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
|
|
|
|
if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
|
|
|
|
DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
|
|
|
|
"It is not fully implemented.\n", index<<2);
|
|
|
|
}
|
|
|
|
macreg_writeops[index](s, index, val);
|
|
|
|
} else { /* "flag needed" bit is set, but the flag is not active */
|
|
|
|
DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n",
|
|
|
|
index<<2);
|
|
|
|
}
|
2010-11-11 16:10:04 +01:00
|
|
|
} else if (index < NREADOPS && macreg_readops[index]) {
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n",
|
|
|
|
index<<2, val);
|
2010-11-11 16:10:04 +01:00
|
|
|
} else {
|
2011-08-08 15:09:08 +02:00
|
|
|
DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
|
2008-02-03 03:20:18 +01:00
|
|
|
index<<2, val);
|
2010-11-11 16:10:04 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2011-08-08 15:09:08 +02:00
|
|
|
static uint64_t
|
2012-10-23 12:30:10 +02:00
|
|
|
e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
2008-12-01 19:59:50 +01:00
|
|
|
unsigned int index = (addr & 0x1ffff) >> 2;
|
2008-02-03 03:20:18 +01:00
|
|
|
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
if (index < NREADOPS && macreg_readops[index]) {
|
|
|
|
if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
|
|
|
|
|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
|
|
|
|
if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
|
|
|
|
DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
|
|
|
|
"It is not fully implemented.\n", index<<2);
|
|
|
|
}
|
|
|
|
return macreg_readops[index](s, index);
|
|
|
|
} else { /* "flag needed" bit is set, but the flag is not active */
|
|
|
|
DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n",
|
|
|
|
index<<2);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
|
2008-03-13 20:18:26 +01:00
|
|
|
}
|
2008-02-03 03:20:18 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-08 15:09:08 +02:00
|
|
|
static const MemoryRegionOps e1000_mmio_ops = {
|
|
|
|
.read = e1000_mmio_read,
|
|
|
|
.write = e1000_mmio_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t e1000_io_read(void *opaque, hwaddr addr,
|
2011-08-08 15:09:08 +02:00
|
|
|
unsigned size)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2011-08-08 15:09:08 +02:00
|
|
|
E1000State *s = opaque;
|
|
|
|
|
|
|
|
(void)s;
|
|
|
|
return 0;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void e1000_io_write(void *opaque, hwaddr addr,
|
2011-08-08 15:09:08 +02:00
|
|
|
uint64_t val, unsigned size)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2011-08-08 15:09:08 +02:00
|
|
|
E1000State *s = opaque;
|
|
|
|
|
|
|
|
(void)s;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2011-08-08 15:09:08 +02:00
|
|
|
static const MemoryRegionOps e1000_io_ops = {
|
|
|
|
.read = e1000_io_read,
|
|
|
|
.write = e1000_io_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2009-10-19 20:06:05 +02:00
|
|
|
static bool is_version_1(void *opaque, int version_id)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2009-10-19 20:06:05 +02:00
|
|
|
return version_id == 1;
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2017-09-25 13:29:12 +02:00
|
|
|
static int e1000_pre_save(void *opaque)
|
2013-02-05 20:00:21 +01:00
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
NetClientState *nc = qemu_get_queue(s->nic);
|
2013-02-14 18:11:27 +01:00
|
|
|
|
2013-02-05 20:00:21 +01:00
|
|
|
/*
|
2014-06-19 17:55:33 +02:00
|
|
|
* If link is down and auto-negotiation is supported and ongoing,
|
|
|
|
* complete auto-negotiation immediately. This allows us to look
|
|
|
|
* at MII_SR_AUTONEG_COMPLETE to infer link status on load.
|
2013-02-05 20:00:21 +01:00
|
|
|
*/
|
2014-06-19 21:40:51 +02:00
|
|
|
if (nc->link_down && have_autoneg(s)) {
|
|
|
|
s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
|
2013-02-05 20:00:21 +01:00
|
|
|
}
|
2017-09-25 13:29:12 +02:00
|
|
|
|
2018-03-28 18:36:29 +02:00
|
|
|
/* Decide which set of props to migrate in the main structure */
|
|
|
|
if (chkflag(TSO) || !s->use_tso_for_migration) {
|
|
|
|
/* Either we're migrating with the extra subsection, in which
|
|
|
|
* case the mig_props is always 'props' OR
|
|
|
|
* we've not got the subsection, but 'props' was the last
|
|
|
|
* updated.
|
|
|
|
*/
|
|
|
|
s->mig_props = s->tx.props;
|
|
|
|
} else {
|
|
|
|
/* We're not using the subsection, and 'tso_props' was
|
|
|
|
* the last updated.
|
|
|
|
*/
|
|
|
|
s->mig_props = s->tx.tso_props;
|
|
|
|
}
|
2017-09-25 13:29:12 +02:00
|
|
|
return 0;
|
2013-02-05 20:00:21 +01:00
|
|
|
}
|
|
|
|
|
2012-09-28 04:06:01 +02:00
|
|
|
static int e1000_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
2013-01-30 12:12:22 +01:00
|
|
|
NetClientState *nc = qemu_get_queue(s->nic);
|
2012-09-28 04:06:01 +02:00
|
|
|
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
if (!chkflag(MIT)) {
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
s->mac_reg[ITR] = s->mac_reg[RDTR] = s->mac_reg[RADV] =
|
|
|
|
s->mac_reg[TADV] = 0;
|
|
|
|
s->mit_irq_level = false;
|
|
|
|
}
|
|
|
|
s->mit_ide = 0;
|
2019-07-10 05:52:53 +02:00
|
|
|
s->mit_timer_on = true;
|
|
|
|
timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
|
2012-09-28 04:06:01 +02:00
|
|
|
/* nc.link_down can't be migrated, so infer link_down according
|
2013-02-05 20:00:21 +01:00
|
|
|
* to link status bit in mac_reg[STATUS].
|
|
|
|
* Alternatively, restart link negotiation if it was in progress. */
|
2013-01-30 12:12:22 +01:00
|
|
|
nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;
|
2013-02-14 18:11:27 +01:00
|
|
|
|
2014-06-19 21:40:51 +02:00
|
|
|
if (have_autoneg(s) &&
|
2013-02-05 20:00:21 +01:00
|
|
|
!(s->phy_reg[PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
|
|
|
|
nc->link_down = false;
|
2014-06-19 21:40:51 +02:00
|
|
|
timer_mod(s->autoneg_timer,
|
|
|
|
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
|
2013-02-05 20:00:21 +01:00
|
|
|
}
|
2012-09-28 04:06:01 +02:00
|
|
|
|
2018-03-28 18:36:28 +02:00
|
|
|
s->tx.props = s->mig_props;
|
2018-03-28 18:36:26 +02:00
|
|
|
if (!s->received_tx_tso) {
|
|
|
|
/* We received only one set of offload data (tx.props)
|
|
|
|
* and haven't got tx.tso_props. The best we can do
|
|
|
|
* is dupe the data.
|
|
|
|
*/
|
2018-03-28 18:36:28 +02:00
|
|
|
s->tx.tso_props = s->mig_props;
|
2018-03-28 18:36:26 +02:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int e1000_tx_tso_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
s->received_tx_tso = true;
|
2012-09-28 04:06:01 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
static bool e1000_mit_state_needed(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
return chkflag(MIT);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
}
|
|
|
|
|
2015-11-11 14:52:40 +01:00
|
|
|
static bool e1000_full_mac_needed(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
|
e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata
about the MAC registers: if a register is accessible, but partly implemented,
or if a register requires a certain compatibility flag in order to be
accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000
so far) but in the future, if more than 6 flags will be needed, the datatype
of this array can simply be swapped for a larger one.
This patch is intended to solve the following current problems:
1) In a scenario of migration between different versions of QEMU, which
differ by the MAC registers implemented in them, some registers need not to
be active if a compatibility flag is set, in order to preserve the machine's
state perfectly for the older version. Checking this for each register
individually, would create a lot of clutter in the code.
2) Some registers are (or may be) only partly implemented (e.g.
placeholders that allow reading and writing, but lack other functions).
In such cases it is better to print a debug warning on read/write attempts.
As above, dealing with this functionality on a per-register level, would
require longer and more messy code.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-11 14:52:41 +01:00
|
|
|
return chkflag(MAC);
|
2015-11-11 14:52:40 +01:00
|
|
|
}
|
|
|
|
|
2018-03-28 18:36:27 +02:00
|
|
|
static bool e1000_tso_state_needed(void *opaque)
|
|
|
|
{
|
|
|
|
E1000State *s = opaque;
|
|
|
|
|
|
|
|
return chkflag(TSO);
|
|
|
|
}
|
|
|
|
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
static const VMStateDescription vmstate_e1000_mit_state = {
|
|
|
|
.name = "e1000/mit_state",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-09-23 14:09:54 +02:00
|
|
|
.needed = e1000_mit_state_needed,
|
2014-04-16 15:32:32 +02:00
|
|
|
.fields = (VMStateField[]) {
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
VMSTATE_UINT32(mac_reg[RDTR], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RADV], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TADV], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[ITR], E1000State),
|
|
|
|
VMSTATE_BOOL(mit_irq_level, E1000State),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2015-11-11 14:52:40 +01:00
|
|
|
static const VMStateDescription vmstate_e1000_full_mac_state = {
|
|
|
|
.name = "e1000/full_mac_state",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.needed = e1000_full_mac_needed,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2018-03-28 18:36:25 +02:00
|
|
|
static const VMStateDescription vmstate_e1000_tx_tso_state = {
|
|
|
|
.name = "e1000/tx_tso_state",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2018-03-28 18:36:27 +02:00
|
|
|
.needed = e1000_tso_state_needed,
|
2018-03-28 18:36:26 +02:00
|
|
|
.post_load = e1000_tx_tso_post_load,
|
2018-03-28 18:36:25 +02:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT8(tx.tso_props.ipcss, E1000State),
|
|
|
|
VMSTATE_UINT8(tx.tso_props.ipcso, E1000State),
|
|
|
|
VMSTATE_UINT16(tx.tso_props.ipcse, E1000State),
|
|
|
|
VMSTATE_UINT8(tx.tso_props.tucss, E1000State),
|
|
|
|
VMSTATE_UINT8(tx.tso_props.tucso, E1000State),
|
|
|
|
VMSTATE_UINT16(tx.tso_props.tucse, E1000State),
|
|
|
|
VMSTATE_UINT32(tx.tso_props.paylen, E1000State),
|
|
|
|
VMSTATE_UINT8(tx.tso_props.hdr_len, E1000State),
|
|
|
|
VMSTATE_UINT16(tx.tso_props.mss, E1000State),
|
|
|
|
VMSTATE_INT8(tx.tso_props.ip, E1000State),
|
|
|
|
VMSTATE_INT8(tx.tso_props.tcp, E1000State),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-10-19 20:06:05 +02:00
|
|
|
static const VMStateDescription vmstate_e1000 = {
|
|
|
|
.name = "e1000",
|
2018-03-28 18:36:25 +02:00
|
|
|
.version_id = 2,
|
2009-10-19 20:06:05 +02:00
|
|
|
.minimum_version_id = 1,
|
2013-02-05 20:00:21 +01:00
|
|
|
.pre_save = e1000_pre_save,
|
2012-09-28 04:06:01 +02:00
|
|
|
.post_load = e1000_post_load,
|
2014-04-16 15:32:32 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2013-06-30 12:55:52 +02:00
|
|
|
VMSTATE_PCI_DEVICE(parent_obj, E1000State),
|
2009-10-19 20:06:05 +02:00
|
|
|
VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
|
|
|
|
VMSTATE_UNUSED(4), /* Was mmio_base. */
|
|
|
|
VMSTATE_UINT32(rxbuf_size, E1000State),
|
|
|
|
VMSTATE_UINT32(rxbuf_min_shift, E1000State),
|
|
|
|
VMSTATE_UINT32(eecd_state.val_in, E1000State),
|
|
|
|
VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
|
|
|
|
VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
|
|
|
|
VMSTATE_UINT16(eecd_state.reading, E1000State),
|
|
|
|
VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
|
2018-03-28 18:36:28 +02:00
|
|
|
VMSTATE_UINT8(mig_props.ipcss, E1000State),
|
|
|
|
VMSTATE_UINT8(mig_props.ipcso, E1000State),
|
|
|
|
VMSTATE_UINT16(mig_props.ipcse, E1000State),
|
|
|
|
VMSTATE_UINT8(mig_props.tucss, E1000State),
|
|
|
|
VMSTATE_UINT8(mig_props.tucso, E1000State),
|
|
|
|
VMSTATE_UINT16(mig_props.tucse, E1000State),
|
|
|
|
VMSTATE_UINT32(mig_props.paylen, E1000State),
|
|
|
|
VMSTATE_UINT8(mig_props.hdr_len, E1000State),
|
|
|
|
VMSTATE_UINT16(mig_props.mss, E1000State),
|
2009-10-19 20:06:05 +02:00
|
|
|
VMSTATE_UINT16(tx.size, E1000State),
|
|
|
|
VMSTATE_UINT16(tx.tso_frames, E1000State),
|
2017-11-15 00:23:33 +01:00
|
|
|
VMSTATE_UINT8(tx.sum_needed, E1000State),
|
2018-03-28 18:36:28 +02:00
|
|
|
VMSTATE_INT8(mig_props.ip, E1000State),
|
|
|
|
VMSTATE_INT8(mig_props.tcp, E1000State),
|
2009-10-19 20:06:05 +02:00
|
|
|
VMSTATE_BUFFER(tx.header, E1000State),
|
|
|
|
VMSTATE_BUFFER(tx.data, E1000State),
|
|
|
|
VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
|
|
|
|
VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
|
|
|
|
VMSTATE_UINT32(mac_reg[CTRL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[EECD], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[EERD], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[GPRC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[GPTC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[ICR], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[ICS], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[IMC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[IMS], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[MANC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[MDIC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[MPC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[PBA], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RCTL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RDH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[RDT], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[STATUS], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[SWSM], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TCTL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TDH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TDT], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TORH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TORL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TOTH], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TOTL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TPR], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TPT], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[WUFC], E1000State),
|
|
|
|
VMSTATE_UINT32(mac_reg[VET], E1000State),
|
|
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
|
|
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
|
|
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
|
|
|
|
VMSTATE_END_OF_LIST()
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
},
|
2014-09-23 14:09:54 +02:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_e1000_mit_state,
|
2015-11-11 14:52:40 +01:00
|
|
|
&vmstate_e1000_full_mac_state,
|
2018-03-28 18:36:25 +02:00
|
|
|
&vmstate_e1000_tx_tso_state,
|
2014-09-23 14:09:54 +02:00
|
|
|
NULL
|
2009-10-19 20:06:05 +02:00
|
|
|
}
|
|
|
|
};
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2014-06-02 15:33:27 +02:00
|
|
|
/*
|
|
|
|
* EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102.
|
|
|
|
* Note: A valid DevId will be inserted during pci_e1000_init().
|
|
|
|
*/
|
2008-10-02 20:24:21 +02:00
|
|
|
static const uint16_t e1000_eeprom_template[64] = {
|
2008-02-03 03:20:18 +01:00
|
|
|
0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
|
2014-06-02 15:33:27 +02:00
|
|
|
0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,
|
2008-02-03 03:20:18 +01:00
|
|
|
0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
|
|
|
|
0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
|
|
|
|
0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
|
|
|
|
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
|
|
|
0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
|
|
|
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* PCI interface */
|
|
|
|
|
|
|
|
static void
|
2011-08-08 15:09:08 +02:00
|
|
|
e1000_mmio_setup(E1000State *d)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2008-12-09 21:09:57 +01:00
|
|
|
int i;
|
|
|
|
const uint32_t excluded_regs[] = {
|
|
|
|
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
|
|
|
|
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
|
|
|
|
};
|
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&d->mmio, OBJECT(d), &e1000_mmio_ops, d,
|
|
|
|
"e1000-mmio", PNPMMIO_SIZE);
|
2011-08-08 15:09:08 +02:00
|
|
|
memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
|
2008-12-09 21:09:57 +01:00
|
|
|
for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
|
2011-08-08 15:09:08 +02:00
|
|
|
memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
|
|
|
|
excluded_regs[i+1] - excluded_regs[i] - 4);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&d->io, OBJECT(d), &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
|
2008-02-03 03:20:18 +01:00
|
|
|
}
|
|
|
|
|
2012-07-04 06:39:27 +02:00
|
|
|
static void
|
2009-02-11 16:21:22 +01:00
|
|
|
pci_e1000_uninit(PCIDevice *dev)
|
|
|
|
{
|
2013-06-24 08:50:30 +02:00
|
|
|
E1000State *d = E1000(dev);
|
2009-02-11 16:21:22 +01:00
|
|
|
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_del(d->autoneg_timer);
|
|
|
|
timer_free(d->autoneg_timer);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
timer_del(d->mit_timer);
|
|
|
|
timer_free(d->mit_timer);
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
timer_del(d->flush_queue_timer);
|
|
|
|
timer_free(d->flush_queue_timer);
|
2013-01-30 12:12:24 +01:00
|
|
|
qemu_del_nic(d->nic);
|
2009-02-11 16:21:22 +01:00
|
|
|
}
|
|
|
|
|
2009-11-25 19:49:12 +01:00
|
|
|
static NetClientInfo net_e1000_info = {
|
qapi: Change Netdev into a flat union
This is a mostly-mechanical conversion that creates a new flat
union 'Netdev' QAPI type that covers all the branches of the
former 'NetClientOptions' simple union, where the branches are
now listed in a new 'NetClientDriver' enum rather than generated
from the simple union. The existence of a flat union has no
change to the command line syntax accepted for new code, and
will make it possible for a future patch to switch the QMP
command to parse a boxed union for no change to valid QMP; but
it does have some ripple effect on the C code when dealing with
the new types.
While making the conversion, note that the 'NetLegacy' type
remains unchanged: it applies only to legacy command line options,
and will not be ported to QMP, so it should remain a wrapper
around a simple union; to avoid confusion, the type named
'NetClientOptions' is now gone, and we introduce 'NetLegacyOptions'
in its place. Then, in the C code, we convert from NetLegacy to
Netdev as soon as possible, so that the bulk of the net stack
only has to deal with one QAPI type, not two. Note that since
the old legacy code always rejected 'hubport', we can just omit
that branch from the new 'NetLegacyOptions' simple union.
Based on an idea originally by Zoltán Kővágó <DirtY.iCE.hu@gmail.com>:
Message-Id: <01a527fbf1a5de880091f98cf011616a78adeeee.1441627176.git.DirtY.iCE.hu@gmail.com>
although the sed script in that patch no longer applies due to
other changes in the tree since then, and I also did some manual
cleanups (such as fixing whitespace to keep checkpatch happy).
Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <1468468228-27827-13-git-send-email-eblake@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Fixup from Eric squashed in]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-07-14 05:50:23 +02:00
|
|
|
.type = NET_CLIENT_DRIVER_NIC,
|
2009-11-25 19:49:12 +01:00
|
|
|
.size = sizeof(NICState),
|
|
|
|
.can_receive = e1000_can_receive,
|
|
|
|
.receive = e1000_receive,
|
2013-09-12 10:47:37 +02:00
|
|
|
.receive_iov = e1000_receive_iov,
|
2009-11-25 19:49:12 +01:00
|
|
|
.link_status_changed = e1000_set_link_status,
|
|
|
|
};
|
|
|
|
|
2014-12-01 19:06:52 +01:00
|
|
|
static void e1000_write_config(PCIDevice *pci_dev, uint32_t address,
|
|
|
|
uint32_t val, int len)
|
|
|
|
{
|
|
|
|
E1000State *s = E1000(pci_dev);
|
|
|
|
|
|
|
|
pci_default_write_config(pci_dev, address, val, len);
|
|
|
|
|
|
|
|
if (range_covers_byte(address, len, PCI_COMMAND) &&
|
|
|
|
(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
|
|
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
|
2008-02-03 03:20:18 +01:00
|
|
|
{
|
2013-06-24 08:50:30 +02:00
|
|
|
DeviceState *dev = DEVICE(pci_dev);
|
|
|
|
E1000State *d = E1000(pci_dev);
|
2008-02-03 03:20:18 +01:00
|
|
|
uint8_t *pci_conf;
|
2009-10-21 15:25:31 +02:00
|
|
|
uint8_t *macaddr;
|
2008-04-22 01:02:48 +02:00
|
|
|
|
2014-12-01 19:06:52 +01:00
|
|
|
pci_dev->config_write = e1000_write_config;
|
|
|
|
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_conf = pci_dev->config;
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2009-12-10 14:23:59 +01:00
|
|
|
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
|
|
|
|
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2011-09-11 12:40:23 +02:00
|
|
|
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2011-08-08 15:09:08 +02:00
|
|
|
e1000_mmio_setup(d);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2013-06-30 12:55:52 +02:00
|
|
|
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2009-10-21 15:25:31 +02:00
|
|
|
qemu_macaddr_default_if_unset(&d->conf.macaddr);
|
|
|
|
macaddr = d->conf.macaddr.a;
|
2016-06-01 10:23:44 +02:00
|
|
|
|
|
|
|
e1000x_core_prepare_eeprom(d->eeprom_data,
|
|
|
|
e1000_eeprom_template,
|
|
|
|
sizeof(e1000_eeprom_template),
|
|
|
|
PCI_DEVICE_GET_CLASS(pci_dev)->device_id,
|
|
|
|
macaddr);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2009-11-25 19:49:12 +01:00
|
|
|
d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
|
2013-06-24 08:50:30 +02:00
|
|
|
object_get_typename(OBJECT(d)), dev->id, d);
|
2008-02-03 03:20:18 +01:00
|
|
|
|
2013-01-30 12:12:22 +01:00
|
|
|
qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr);
|
2010-12-08 12:35:05 +01:00
|
|
|
|
2013-08-21 17:03:08 +02:00
|
|
|
d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d);
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d);
|
e1000: Delay flush queue when receive RCTL
Due to too early RCT0 interrput, win10x32 may hang on booting.
This problem can be reproduced by doing power cycle on win10x32 guest.
In our environment, we have 10 win10x32 and stress power cycle.
The problem will happen about 20 rounds.
Below shows some log with comment:
The normal case:
22831@1551928392.984687:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985655:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928392.985801:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.056710:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.077548:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
22831@1551928393.102974:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
22831@1551928393.103267:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 0, ICR 2, IMR 9d <- unmask interrupt
e1000: RCTL: 255, mac_reg[RCTL] = 0x48002
e1000: set_ics 80, ICR 2, IMR 9d <- interrupt and work!
...
The bad case:
27744@1551930483.117766:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.118398:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.198063:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.218675:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: set_ics 0, ICR 0, IMR 0
e1000: ICR read: 0
e1000: set_ics 2, ICR 0, IMR 0
e1000: set_ics 2, ICR 2, IMR 0
e1000: RCTL: 0, mac_reg[RCTL] = 0x0
27744@1551930483.241768:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
27744@1551930483.241979:e1000x_rx_disabled Received packet dropped
because receive is disabled RCTL = 0
e1000: RCTL: 255, mac_reg[RCTL] = 0x40002 <- win10x32 says it can handle
RX now
e1000: set_ics 80, ICR 2, IMR 0 <- flush queue (caused by setting RCTL)
e1000: set_ics 0, ICR 82, IMR 9d <- unmask interrupt and because 0x82&0x9d
!= 0 generate interrupt, hang on here...
To workaround this problem, simply delay flush queue. Also stop receiving
when timer is going to run.
Tested on CentOS, Win7SP1x64 and Win10x32.
Signed-off-by: yuchenlin <yuchenlin@synology.com>
Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-03-13 07:56:49 +01:00
|
|
|
d->flush_queue_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
|
|
|
|
e1000_flush_queue_timer, d);
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
2009-02-11 16:19:52 +01:00
|
|
|
|
2009-10-21 15:25:31 +02:00
|
|
|
static void qdev_e1000_reset(DeviceState *dev)
|
|
|
|
{
|
2013-06-24 08:50:30 +02:00
|
|
|
E1000State *d = E1000(dev);
|
2009-10-21 15:25:31 +02:00
|
|
|
e1000_reset(d);
|
|
|
|
}
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static Property e1000_properties[] = {
|
|
|
|
DEFINE_NIC_PROPERTIES(E1000State, conf),
|
2013-02-14 18:11:27 +01:00
|
|
|
DEFINE_PROP_BIT("autonegotiation", E1000State,
|
|
|
|
compat_flags, E1000_FLAG_AUTONEG_BIT, true),
|
e1000: add interrupt mitigation support
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulated (RDTR is only used to validate RADV, according to the e1000 specs).
RADV, TADV, TIDV and RDTR registers make up the older e1000 mitigation
mechanism and would need a timer each to be completely emulated. However,
a single timer has been used in order to reach a good compromise between
emulation accuracy and simplicity/efficiency.
The implemented mechanism can be enabled/disabled specifying the command
line e1000-specific boolean parameter "mitigation", e.g.
qemu-system-x86_64 -device e1000,mitigation=on,... ...
For more information, see the Software developer's manual at
http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf.
Interrupt mitigation boosts performance when the guest suffers from
an high interrupt rate (i.e. receiving short UDP packets at high packet
rate). For some numerical results see the following link
http://info.iet.unipi.it/~luigi/papers/20130520-rizzo-vm.pdf
Signed-off-by: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de> (for pc-* machines)
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-02 18:30:52 +02:00
|
|
|
DEFINE_PROP_BIT("mitigation", E1000State,
|
|
|
|
compat_flags, E1000_FLAG_MIT_BIT, true),
|
2015-11-11 14:52:47 +01:00
|
|
|
DEFINE_PROP_BIT("extra_mac_registers", E1000State,
|
|
|
|
compat_flags, E1000_FLAG_MAC_BIT, true),
|
2018-03-28 18:36:27 +02:00
|
|
|
DEFINE_PROP_BIT("migrate_tso_props", E1000State,
|
|
|
|
compat_flags, E1000_FLAG_TSO_BIT, true),
|
2011-12-04 19:22:06 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2014-06-02 15:33:27 +02:00
|
|
|
typedef struct E1000Info {
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const char *name;
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uint16_t device_id;
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uint8_t revision;
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uint16_t phy_id2;
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} E1000Info;
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2011-12-04 19:22:06 +01:00
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static void e1000_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-04 19:22:06 +01:00
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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2014-06-02 15:33:27 +02:00
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E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
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const E1000Info *info = data;
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2011-12-04 19:22:06 +01:00
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2015-01-19 15:52:30 +01:00
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k->realize = pci_e1000_realize;
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2011-12-04 19:22:06 +01:00
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k->exit = pci_e1000_uninit;
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2013-02-26 17:46:11 +01:00
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k->romfile = "efi-e1000.rom";
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2011-12-04 19:22:06 +01:00
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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2014-06-02 15:33:27 +02:00
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k->device_id = info->device_id;
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k->revision = info->revision;
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e->phy_id2 = info->phy_id2;
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2011-12-04 19:22:06 +01:00
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k->class_id = PCI_CLASS_NETWORK_ETHERNET;
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2013-07-29 16:17:45 +02:00
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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2011-12-08 04:34:16 +01:00
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dc->desc = "Intel Gigabit Ethernet";
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dc->reset = qdev_e1000_reset;
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dc->vmsd = &vmstate_e1000;
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dc->props = e1000_properties;
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2011-12-04 19:22:06 +01:00
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}
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2014-10-07 10:00:13 +02:00
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static void e1000_instance_init(Object *obj)
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{
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E1000State *n = E1000(obj);
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device_add_bootindex_property(obj, &n->conf.bootindex,
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"bootindex", "/ethernet-phy@0",
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DEVICE(n), NULL);
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}
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2014-06-02 15:33:27 +02:00
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static const TypeInfo e1000_base_info = {
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.name = TYPE_E1000_BASE,
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2011-12-08 04:34:16 +01:00
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(E1000State),
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2014-10-07 10:00:13 +02:00
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.instance_init = e1000_instance_init,
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2014-06-02 15:33:27 +02:00
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.class_size = sizeof(E1000BaseClass),
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.abstract = true,
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2017-09-27 21:56:34 +02:00
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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2014-06-02 15:33:27 +02:00
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};
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static const E1000Info e1000_devices[] = {
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{
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2015-09-28 07:37:26 +02:00
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.name = "e1000",
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2014-06-02 15:33:27 +02:00
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.device_id = E1000_DEV_ID_82540EM,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
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},
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{
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.name = "e1000-82544gc",
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.device_id = E1000_DEV_ID_82544GC_COPPER,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_82544x,
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},
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{
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.name = "e1000-82545em",
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.device_id = E1000_DEV_ID_82545EM_COPPER,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
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},
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};
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2012-02-09 15:20:55 +01:00
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static void e1000_register_types(void)
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2009-05-14 23:35:07 +02:00
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{
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2014-06-02 15:33:27 +02:00
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int i;
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type_register_static(&e1000_base_info);
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for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) {
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const E1000Info *info = &e1000_devices[i];
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TypeInfo type_info = {};
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type_info.name = info->name;
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type_info.parent = TYPE_E1000_BASE;
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type_info.class_data = (void *)info;
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type_info.class_init = e1000_class_init;
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2014-10-07 10:00:13 +02:00
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type_info.instance_init = e1000_instance_init;
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2014-06-02 15:33:27 +02:00
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type_register(&type_info);
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}
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2008-02-03 03:20:18 +01:00
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}
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2009-05-14 23:35:07 +02:00
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2012-02-09 15:20:55 +01:00
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type_init(e1000_register_types)
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