2006-05-13 18:11:23 +02:00
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/*
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* QEMU PREP PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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2012-05-26 19:14:52 +02:00
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* Copyright (c) 2011-2013 Andreas Färber
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2007-09-16 23:08:06 +02:00
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*
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2006-05-13 18:11:23 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 19:16:58 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/i386/pc.h"
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2013-11-05 00:09:45 +01:00
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#include "hw/loader.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2013-11-05 00:09:45 +01:00
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#include "elf.h"
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2006-05-13 18:11:23 +02:00
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2012-05-26 19:14:52 +02:00
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#define TYPE_RAVEN_PCI_DEVICE "raven"
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2012-08-20 19:08:04 +02:00
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#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
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2012-05-26 19:14:52 +02:00
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#define RAVEN_PCI_DEVICE(obj) \
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OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
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typedef struct RavenPCIState {
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PCIDevice dev;
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2013-11-05 00:09:45 +01:00
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uint32_t elf_machine;
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char *bios_name;
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MemoryRegion bios;
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2012-05-26 19:14:52 +02:00
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} RavenPCIState;
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2012-08-20 19:08:04 +02:00
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#define RAVEN_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
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2012-01-03 02:42:46 +01:00
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typedef struct PRePPCIState {
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2012-08-20 19:08:09 +02:00
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PCIHostState parent_obj;
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2012-08-20 19:08:04 +02:00
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2013-11-05 00:09:44 +01:00
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qemu_irq irq[PCI_NUM_PINS];
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2012-05-26 19:14:52 +02:00
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PCIBus pci_bus;
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2014-03-17 23:00:20 +01:00
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AddressSpace pci_io_as;
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2014-03-17 23:00:21 +01:00
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MemoryRegion pci_io;
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2014-03-17 23:00:20 +01:00
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MemoryRegion pci_io_non_contiguous;
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2014-03-17 23:00:22 +01:00
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MemoryRegion pci_memory;
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2014-03-17 23:00:19 +01:00
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MemoryRegion pci_intack;
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2014-03-17 23:00:23 +01:00
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MemoryRegion bm;
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MemoryRegion bm_ram_alias;
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MemoryRegion bm_pci_memory_alias;
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AddressSpace bm_as;
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2012-05-26 19:14:52 +02:00
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RavenPCIState pci_dev;
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2014-03-17 23:00:20 +01:00
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int contiguous_map;
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2012-01-03 02:42:46 +01:00
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} PREPPCIState;
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2006-05-13 18:11:23 +02:00
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2013-11-05 00:09:45 +01:00
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#define BIOS_SIZE (1024 * 1024)
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2014-03-17 23:00:25 +01:00
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static inline uint32_t raven_pci_io_config(hwaddr addr)
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2006-05-13 18:11:23 +02:00
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{
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int i;
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2012-08-20 19:08:04 +02:00
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for (i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0) {
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2006-05-13 18:11:23 +02:00
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break;
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2012-08-20 19:08:04 +02:00
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}
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2006-05-13 18:11:23 +02:00
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}
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return (addr & 0x7ff) | (i << 11);
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}
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2014-03-17 23:00:25 +01:00
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static void raven_pci_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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2006-05-13 18:11:23 +02:00
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{
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PREPPCIState *s = opaque;
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2012-08-20 19:08:09 +02:00
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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2014-03-17 23:00:25 +01:00
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pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
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2006-05-13 18:11:23 +02:00
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}
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2014-03-17 23:00:25 +01:00
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static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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2006-05-13 18:11:23 +02:00
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{
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PREPPCIState *s = opaque;
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2012-08-20 19:08:09 +02:00
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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2014-03-17 23:00:25 +01:00
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return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
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2006-05-13 18:11:23 +02:00
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}
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2014-03-17 23:00:25 +01:00
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static const MemoryRegionOps raven_pci_io_ops = {
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.read = raven_pci_io_read,
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.write = raven_pci_io_write,
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2012-01-12 03:44:42 +01:00
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.endianness = DEVICE_LITTLE_ENDIAN,
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2006-05-13 18:11:23 +02:00
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};
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2014-03-17 23:00:25 +01:00
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static uint64_t raven_intack_read(void *opaque, hwaddr addr,
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unsigned int size)
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2012-04-14 22:48:37 +02:00
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{
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return pic_read_irq(isa_pic);
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}
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2014-03-17 23:00:25 +01:00
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static const MemoryRegionOps raven_intack_ops = {
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.read = raven_intack_read,
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2012-04-14 22:48:37 +02:00
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.valid = {
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.max_access_size = 1,
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},
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};
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2014-03-17 23:00:20 +01:00
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static inline hwaddr raven_io_address(PREPPCIState *s,
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hwaddr addr)
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{
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if (s->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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/* FIXME: handle endianness switch */
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return addr;
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}
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static uint64_t raven_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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2015-04-26 17:49:24 +02:00
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address_space_read(&s->pci_io_as, addr + 0x80000000,
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MEMTXATTRS_UNSPECIFIED, buf, size);
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2014-03-17 23:00:20 +01:00
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if (size == 1) {
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return buf[0];
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} else if (size == 2) {
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2014-04-08 17:51:11 +02:00
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return lduw_le_p(buf);
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2014-03-17 23:00:20 +01:00
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} else if (size == 4) {
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2014-04-08 17:51:11 +02:00
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return ldl_le_p(buf);
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2014-03-17 23:00:20 +01:00
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} else {
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g_assert_not_reached();
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}
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}
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static void raven_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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if (size == 1) {
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buf[0] = val;
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} else if (size == 2) {
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2014-04-08 17:51:11 +02:00
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stw_le_p(buf, val);
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2014-03-17 23:00:20 +01:00
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} else if (size == 4) {
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2014-04-08 17:51:11 +02:00
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stl_le_p(buf, val);
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2014-03-17 23:00:20 +01:00
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} else {
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g_assert_not_reached();
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}
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2015-04-26 17:49:24 +02:00
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address_space_write(&s->pci_io_as, addr + 0x80000000,
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MEMTXATTRS_UNSPECIFIED, buf, size);
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2014-03-17 23:00:20 +01:00
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}
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static const MemoryRegionOps raven_io_ops = {
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.read = raven_io_read,
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.write = raven_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.max_access_size = 4,
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.valid.unaligned = true,
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};
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2014-03-17 23:00:25 +01:00
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static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
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2006-05-13 18:11:23 +02:00
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{
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2006-09-24 19:01:44 +02:00
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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2006-09-24 02:16:34 +02:00
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}
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2014-03-17 23:00:25 +01:00
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static void raven_set_irq(void *opaque, int irq_num, int level)
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2006-09-24 02:16:34 +02:00
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{
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2009-08-28 15:28:17 +02:00
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qemu_irq *pic = opaque;
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2012-01-03 02:42:46 +01:00
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qemu_set_irq(pic[irq_num] , level);
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2006-05-13 18:11:23 +02:00
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}
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2014-03-17 23:00:23 +01:00
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static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
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int devfn)
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{
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PREPPCIState *s = opaque;
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return &s->bm_as;
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}
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2014-03-17 23:00:20 +01:00
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static void raven_change_gpio(void *opaque, int n, int level)
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{
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PREPPCIState *s = opaque;
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s->contiguous_map = level;
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}
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2013-01-16 15:45:34 +01:00
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static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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2006-05-13 18:11:23 +02:00
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{
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2013-01-16 15:45:34 +01:00
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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2012-08-20 19:08:08 +02:00
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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2012-08-20 19:08:04 +02:00
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
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2012-01-03 02:42:46 +01:00
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MemoryRegion *address_space_mem = get_system_memory();
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int i;
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2013-11-05 00:09:44 +01:00
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for (i = 0; i < PCI_NUM_PINS; i++) {
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2012-01-03 02:42:46 +01:00
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sysbus_init_irq(dev, &s->irq[i]);
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}
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2006-05-13 18:11:23 +02:00
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2014-03-17 23:00:20 +01:00
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qdev_init_gpio_in(d, raven_change_gpio, 1);
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2014-03-17 23:00:25 +01:00
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pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
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PCI_NUM_PINS);
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2006-05-13 18:11:23 +02:00
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2014-03-17 23:00:24 +01:00
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4);
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2014-03-17 23:00:21 +01:00
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memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
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2011-07-24 16:47:18 +02:00
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2014-03-17 23:00:24 +01:00
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
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"pci-conf-data", 4);
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2014-03-17 23:00:21 +01:00
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memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
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2006-05-13 18:11:23 +02:00
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2014-03-17 23:00:25 +01:00
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memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
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"pciio", 0x00400000);
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2012-01-03 02:42:46 +01:00
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memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
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2006-05-13 18:11:23 +02:00
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2014-03-17 23:00:25 +01:00
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memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
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2014-03-17 23:00:19 +01:00
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"pci-intack", 1);
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
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2012-01-03 01:50:07 +01:00
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2012-05-26 19:14:52 +02:00
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/* TODO Remove once realize propagates to child devices. */
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2013-01-16 15:45:34 +01:00
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object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
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2012-05-26 19:14:52 +02:00
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}
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static void raven_pcihost_initfn(Object *obj)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
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MemoryRegion *address_space_mem = get_system_memory();
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DeviceState *pci_dev;
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2014-03-17 23:00:21 +01:00
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memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
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2014-03-17 23:00:20 +01:00
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memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
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"pci-io-non-contiguous", 0x00800000);
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2014-04-01 23:19:15 +02:00
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memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
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2014-03-17 23:00:21 +01:00
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address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
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2014-03-17 23:00:20 +01:00
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/* CPU address space */
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2014-03-17 23:00:21 +01:00
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memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
|
2014-03-17 23:00:20 +01:00
|
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memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
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&s->pci_io_non_contiguous, 1);
|
2014-03-17 23:00:22 +01:00
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memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
|
2013-08-23 20:23:55 +02:00
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|
pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
|
2014-03-17 23:00:22 +01:00
|
|
|
&s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
|
2014-03-17 23:00:21 +01:00
|
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2014-03-17 23:00:23 +01:00
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/* Bus master address space */
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|
|
memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
|
|
|
|
memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
|
|
|
|
&s->pci_memory, 0,
|
|
|
|
memory_region_size(&s->pci_memory));
|
|
|
|
memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
|
|
|
|
get_system_memory(), 0, 0x80000000);
|
|
|
|
memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
|
|
|
|
memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
|
|
|
|
address_space_init(&s->bm_as, &s->bm, "raven-bm");
|
|
|
|
pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
|
|
|
|
|
2012-05-26 19:14:52 +02:00
|
|
|
h->bus = &s->pci_bus;
|
|
|
|
|
2013-08-23 19:37:12 +02:00
|
|
|
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
|
2012-05-26 19:14:52 +02:00
|
|
|
pci_dev = DEVICE(&s->pci_dev);
|
|
|
|
qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
|
|
|
|
object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
|
|
|
|
NULL);
|
|
|
|
qdev_prop_set_bit(pci_dev, "multifunction", false);
|
2012-01-03 01:50:07 +01:00
|
|
|
}
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void raven_realize(PCIDevice *d, Error **errp)
|
2012-01-03 01:50:07 +01:00
|
|
|
{
|
2013-11-05 00:09:45 +01:00
|
|
|
RavenPCIState *s = RAVEN_PCI_DEVICE(d);
|
|
|
|
char *filename;
|
|
|
|
int bios_size = -1;
|
|
|
|
|
2006-05-13 18:11:23 +02:00
|
|
|
d->config[0x0C] = 0x08; // cache_line_size
|
|
|
|
d->config[0x0D] = 0x10; // latency_timer
|
|
|
|
d->config[0x34] = 0x00; // capabilities_pointer
|
|
|
|
|
2014-09-09 07:27:55 +02:00
|
|
|
memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2013-11-05 00:09:45 +01:00
|
|
|
memory_region_set_readonly(&s->bios, true);
|
|
|
|
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
|
|
|
|
&s->bios);
|
|
|
|
vmstate_register_ram_global(&s->bios);
|
|
|
|
if (s->bios_name) {
|
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
|
|
|
|
if (filename) {
|
|
|
|
if (s->elf_machine != EM_NONE) {
|
|
|
|
bios_size = load_elf(filename, NULL, NULL, NULL,
|
2016-03-04 12:30:21 +01:00
|
|
|
NULL, NULL, 1, s->elf_machine, 0, 0);
|
2013-11-05 00:09:45 +01:00
|
|
|
}
|
|
|
|
if (bios_size < 0) {
|
|
|
|
bios_size = get_image_size(filename);
|
|
|
|
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
|
|
|
|
hwaddr bios_addr;
|
|
|
|
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
|
|
bios_addr = (uint32_t)(-BIOS_SIZE);
|
|
|
|
bios_size = load_image_targphys(filename, bios_addr,
|
|
|
|
bios_size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
2015-12-17 17:35:13 +01:00
|
|
|
/* FIXME should error_setg() */
|
2013-11-05 00:09:45 +01:00
|
|
|
hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
|
|
|
|
}
|
2015-08-26 13:17:18 +02:00
|
|
|
g_free(filename);
|
2013-11-05 00:09:45 +01:00
|
|
|
}
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
2012-01-03 01:50:07 +01:00
|
|
|
|
|
|
|
static const VMStateDescription vmstate_raven = {
|
|
|
|
.name = "raven",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_PCI_DEVICE(dev, RavenPCIState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void raven_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = raven_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
|
|
|
|
k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
|
|
|
|
k->revision = 0x00;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->desc = "PReP Host Bridge - Motorola Raven";
|
|
|
|
dc->vmsd = &vmstate_raven;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
/*
|
2015-12-17 17:35:13 +01:00
|
|
|
* Reason: PCI-facing part of the host bridge, not usable without
|
|
|
|
* the host-facing part, which can't be device_add'ed, yet.
|
|
|
|
* Reason: realize() method uses hw_error().
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
*/
|
|
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo raven_info = {
|
2012-05-26 19:14:52 +02:00
|
|
|
.name = TYPE_RAVEN_PCI_DEVICE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(RavenPCIState),
|
2011-12-04 19:22:06 +01:00
|
|
|
.class_init = raven_class_init,
|
2012-01-03 01:50:07 +01:00
|
|
|
};
|
|
|
|
|
2013-11-05 00:09:45 +01:00
|
|
|
static Property raven_pcihost_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
|
|
|
|
EM_NONE),
|
|
|
|
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void raven_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2013-01-16 15:45:34 +01:00
|
|
|
dc->realize = raven_pcihost_realizefn;
|
2013-11-05 00:09:45 +01:00
|
|
|
dc->props = raven_pcihost_properties;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->fw_name = "pci";
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo raven_pcihost_info = {
|
2012-08-20 19:08:04 +02:00
|
|
|
.name = TYPE_RAVEN_PCI_HOST_BRIDGE,
|
2012-08-20 19:08:08 +02:00
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.instance_size = sizeof(PREPPCIState),
|
2012-05-26 19:14:52 +02:00
|
|
|
.instance_init = raven_pcihost_initfn,
|
2012-01-24 20:12:29 +01:00
|
|
|
.class_init = raven_pcihost_class_init,
|
2012-01-03 02:42:46 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void raven_register_types(void)
|
2012-01-03 01:50:07 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&raven_pcihost_info);
|
|
|
|
type_register_static(&raven_info);
|
2012-01-03 01:50:07 +01:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(raven_register_types)
|