Commit graph

20759 commits

Author SHA1 Message Date
Peter Maydell 4fdd17dd35 target-arm: Convert cp15 crn=10 registers
We RAZ/WI the entire block of crn=10 registers. Note that this
actually covers not just the implementation-defined TLB
lockdown registers but also a number of v7 VMSA memory
attribute registers which we would need to implement to
support TEX remap. We retain the previous QEMU behaviour
in this conversion, though.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:06:05 +00:00
Peter Maydell 08de207bc5 target-arm: Convert cp15 crn=13 registers
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR,
and the ARM946 Trace Process Identifier Register).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:06:01 +00:00
Peter Maydell ecce5c3c90 target-arm: Convert cp15 crn=2 registers
Convert the cp15 crn=2 registers (MMU page table control,
MPU cache control) to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:56 +00:00
Peter Maydell 18032bec5c target-arm: Convert MMU fault status cp15 registers
Convert the MMU fault status and MPU access permission cp15
registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:50 +00:00
Peter Maydell c983fe6cf1 target-arm: Convert cp15 c3 register
Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:44 +00:00
Peter Maydell 6cc7a3aee6 target-arm: Convert generic timer cp15 regs
Convert the (dummy) generic timer cp15 implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:40 +00:00
Peter Maydell 200ac0ef87 target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers to
the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:17 +00:00
Peter Maydell 4d31c59679 target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:54 +00:00
Peter Maydell 7d57f40877 target-arm: Convert WFI/barriers special cases to cp_reginfo
Convert the various WFI and barrier instruction special cases to use
cp_reginfo infrastructure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:32 +00:00
Peter Maydell c326b9796f target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to
use arm_cp_reginfo.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:08 +00:00
Peter Maydell e9aa6c2148 target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:03:44 +00:00
Peter Maydell 2ceb98c007 target-arm: Add register_cp_regs_for_features()
Add new function register_cp_regs_for_features() as a place to
register coprocessor registers dependent on feature flags.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:02:54 +00:00
Peter Maydell e8070a23a8 target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so we
can remove it and the infrastructure it used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:02:01 +00:00
Peter Maydell 9ee703b096 hw/pxa2xx_pic: Convert coprocessor registers to new scheme
Convert the coprocessor access functions for the pxa2xx PIC to the
arm_cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:01:58 +00:00
Peter Maydell e2f8a44d0d hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs
Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the
new arm_cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:01:55 +00:00
Peter Maydell dc2a9045cf hw/pxa2xx: Convert cp14 perf registers to new scheme
Convert the PXA2xx cp14 perf registers from old-style
coprocessor hooks to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:01:52 +00:00
Peter Maydell 4b6a83fb0c target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration of
coprocessor register implementations.

We still fall back to the old-style switch statements pending
complete conversion of all existing registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:01:02 +00:00
Peter Maydell 200bf596b9 target-arm: Fix 11MPCore cache type register value
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore doesn't actually have.
(This causes no problems currently because we over-broadly provide
those ops on all cores, but prevents us correctly narrowing the
block ops down to those cores which actually implement them.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:00:58 +00:00
Crístian Viana 93bfef4c6e Allow machines to configure the QEMU_VERSION that's exposed via hardware
QEMU exposes its version to the guest's hardware and in some cases that is wrong
(e.g. Windows prints messages about driver updates when you switch
the QEMU version).
There is a new field now on the struct QEmuMachine, hw_version, which may
contain the version that the specific machine should report. If that field is
set, then that machine will report that version to the guest.

Signed-off-by: Crístian Viana <vianac@linux.vnet.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19 13:36:56 -05:00
Gleb Natapov 459ae5ea5a Add PIIX4 properties to control PM system states.
This patch adds two things. First it allows QEMU to distinguish between
regular powerdown and S4 powerdown. Later separate QMP notification will
be added for S4 powerdown. Second it allows S3/S4 states to be disabled
from QEMU command line. Some guests known to be broken with regards to
power management, but allow to use it anyway. Using new properties
management will be able to disable S3/S4 for such guests.

Supported system state are passed to a firmware using new fw_cfg file.
The file contains  6 byte array. Each byte represents one system
state. If byte at offset X has its MSB set it means that system state
X is supported and to enter it guest should use the value from lowest 3
bits.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19 13:36:56 -05:00
Anthony Liguori dcff25f2cd make: automatically include dependencies in recursive subdir rules (v2)
I think I understand enough of what's going on in these rules to ensure this is
right.  But I could certainly use a second or third opinion...

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19 13:32:42 -05:00
Avi Kivity 8be74dc0ba configure: fix -enable-debug with newer toolchains
Fedora 17's toolchain wants optimization enabled for _FORTIFY_SOURCE;
so disable _FORTIFY_SOURCE when debugging.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19 13:32:22 -05:00
Peter A. G. Crosthwaite 5e87975c87 arm_boot: Conditionalised DTB command line update
The DTB command line should only be overwritten if the user provides a command
line with -append. Otherwise whatever command line was in the DTB should stay
unchanged.

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter A. G. Crosthwaite 69efc0265f cadence_ttc: changed master clock frequency
Change the timer clock frequency to 133MHz which is correct. the old 2.5MHz
value was for the pre-silicon emulation platform.

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Jim Meyering 5fbe02e8bb cadence_gem: avoid stack-writing buffer-overrun
Use sizeof(rxbuf)-size (not sizeof(rxbuf-size)) as the number
of bytes to clear.  The latter would always clear 4 or 8
bytes, possibly writing beyond the end of that stack buffer.
Alternatively, depending on the value of the "size" parameter,
it could fail to initialize the end of "rxbuf".
Spotted by coverity.

Signed-off-by: Jim Meyering <meyering@redhat.com>
Reviewed-by: Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell c97338dca0 hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit
Add a cast to a logging printf to avoid a compilation failure
if target_phys_addr_t is a 64 bit type. (This is better than
using TARGET_FMT_plx because we really don't need a full
16 digit hex string to print the offset into a device.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
2012-06-19 13:24:44 +00:00
Peter Maydell cff0cfbed5 hw/omap.h: Drop broken MEM_VERBOSE tracing
Remove the MEM_VERBOSE tracing option from omap.h. This worked by
intercepting cpu_register_io_memory() calls; it has been broken
since cpu_register_io_memory() was removed in favour of the
MemoryRegion API.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 1e8cae4dfe hw/armv7m_nvic: Make the NVIC a freestanding class
Rearrange the GIC and NVIC so both are straightforward
subclasses of a common class, rather than having the NVIC
source file textually include arm_gic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 2b518c56a6 hw/arm_gic: Move CPU interface memory region setup into arm_gic_init
Remove more NVIC ifdefs by moving the code to setup the CPU interface
memory regions into the GIC specific arm_gic_init() function rather
than the gic_init() function. Rename the latter to more closely
reflect what it's now actually doing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 84e4fccb7f hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting
Make the minor tweaks to interrupt numbering used by the NVIC
a runtime setting rather than a compile time one, so we can
drop more NVIC ifdefs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 6b9680bb58 hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor
The GIC spec says that the CPU target registers should RAZ/WI
for uniprocessor implementations. Implement this, which also
conveniently lets us drop an NVIC ifdef.

Annoyingly, the 11MPCore's GIC is the odd one out, since
it always has these registers, even in uniprocessor configs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 306a571a2d hw/arm_gic: Add qdev property for GIC revision
GIC behaviour can be different between revision 1 and
2 of the architectural GIC specification; we also have
to handle the legacy 11MPCore GIC, which is different
again in some places. Introduce a qdev property so we
can behave appropriately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell 2a29ddee82 hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers
Implement the NVIC specific register areas using a set of
overlaid MemoryRegions in a container, rather than by having
the arm_gic read/write functions use special purpose callbacks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell b3387ede2f hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset
Move the NVIC specific bits of reset to the NVIC's own
reset function, rather than using ifdefs in the common
arm_gic reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell c48c6522f5 hw/arm_gic: Remove the special casing of NCPU for the NVIC
Drop the special casing of NCPU=1 for the NVIC. This slightly
increases the amount of memory used by its state structure,
but removes some ifdeffery and means we can safely move the
GIC state into a common subclass structure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Peter Maydell acd684280f hw/arm_gic: Remove NVIC ifdefs from gic_state struct
Remove some NVIC ifdefs from the gic_state struct and its
state save/load functions. This means there are some fields
in it which are present for the NVIC but not used, but means
it always has the same layout and can be pulled out into a
common subclass.

Note that the addition of irq_target[] to the save/load
struct for the NVIC requires a vmstate version bump.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-19 13:24:44 +00:00
Andreas Färber 9b574c29c1 arm_boot: Fix typos in comment
mimicing -> mimicking
thei -> the

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 13:24:44 +00:00
Evgeny Voevodin 61558e7a75 ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality.
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.

Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19 12:49:32 +00:00
Anthony Liguori 8aca521512 Merge remote-tracking branch 'afaerber-or/qom-next-2' into staging
* afaerber-or/qom-next-2: (22 commits)
  qom: Push error reporting to object_property_find()
  qdev: Remove qdev_prop_exists()
  qbus: Initialize in standard way
  qbus: Make child devices links
  qdev: Connect busses with their parent devices
  qdev: Convert busses to QEMU Object Model
  qdev: Move SysBus initialization to sysbus.c
  qdev: Use wrapper for qdev_get_path
  qdev: Remove qdev_prop_set_defaults
  qdev: Clean up global properties
  qdev: Move bus properties to abstract superclasses
  qdev: Move bus properties to a separate global
  qdev: Push "type" property up to Object
  arm_l2x0: Rename "type" property to "cache-type"
  m48t59: Rename "type" property to "model"
  qom: Assert that public types have a non-NULL parent field
  qom: Drop type_register_static_alias() macro
  qom: Make Object a type
  qom: Add class_base_init
  qom: Add object_child_foreach()
  ...
2012-06-18 10:35:16 -05:00
Anthony Liguori 664535c31c Merge remote-tracking branch 'qmp/queue/qmp' into staging
* qmp/queue/qmp:
  build: install qmp-commands.txt
  Add rate limiting of RTC_CHANGE, BALLOON_CHANGE & WATCHDOG events
  Add event notification for guest balloon changes
  Fix some more license versions (GPL2+ instead of GPL2)
  monitor: Fix memory leak with readline completion
  qmp: do not include monitor.h from qapi-types-core.h
  qmp: include monitor.h when needed
  kvm: add missing include files
2012-06-18 10:35:13 -05:00
Anthony Liguori 0b0cb9d310 Merge remote-tracking branch 'kwolf/for-anthony' into staging
* kwolf/for-anthony: (39 commits)
  qemu-iotests: add 036 autoclear feature bit test
  qemu-iotests: add qcow2.py set-feature-bit command
  fdc-test: introduced qtest read_without_media
  fdc: fix implied seek while there is no media in drive
  qcow2: fix autoclear image header update
  xen: Don't peek behind the BlockDriverState abstraction
  xen: Don't change -drive if=xen device name during machine init
  block: Replace bdrv_get_format() by bdrv_get_format_name()
  qemu-img: document qed format on qemu-img man page
  qemu-iotests: COW with many AIO requests on the same cluster
  qemu-iotests: Some backing file COW tests
  qcow2: Fix avail_sectors in cluster allocation code
  qcow2: Simplify calculation for COW area at the end
  qcow2: always operate caches in writeback mode
  ide: support enable/disable write cache
  block: always open drivers in writeback mode
  block: add bdrv_set_enable_write_cache
  block: copy enable_write_cache in bdrv_append
  savevm: flush after saving vm state
  block: flush in writethrough mode after writes
  ...
2012-06-18 10:34:59 -05:00
Anthony Liguori df6606f455 Merge remote-tracking branch 'mst/tags/for_anthony' into staging
* mst/tags/for_anthony:
  pci_bridge_dev: fix error path in pci_bridge_dev_initfn()
  qdev: release parent properties on dc->init failure
  msi: Use msi/msix_present more consistently
  msi: Invoke msi/msix_write_config from PCI core
  msi: Guard msi/msix_write_config with msi_present
  msi: Invoke msi/msix_reset from PCI core
  msi: Guard msi_reset with msi_present
  ahci: Clean up reset functions
  intel-hda: Fix reset of MSI function
  ahci: Fix reset of MSI function
  rtl8139: honor RxOverflow flag in can_receive method
  shpc: unparent device before free
2012-06-18 10:18:44 -05:00
Anthony Liguori 49023ff78c Merge remote-tracking branch 'sweil/for-anthony' into staging
* sweil/for-anthony:
  Fix some more license versions (GPL2+ instead of GPL2)
  dump: Fix license version (GPL2+ instead of GPL2)
  configure: Fix build for some versions of glibc (9pfs)
  monitor: Fix memory leak with readline completion
2012-06-18 10:18:26 -05:00
Christian Borntraeger 2fb70f6f17 s390: stop target cpu on sigp initial reset
We must not run the target cpu after an initial reset. This makes
system_reset more reliable for smp guests.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-18 15:32:45 +02:00
Jens Freimann c5854acb75 s390: make kvm_stat work on s390
Add s390_exit_reasons so kvm_stat doesn't crash when called on s390.
Look for 'vendor_id' in /proc/cpuinfo as well, instead of just for
'flags', so we can determine if we run on S390.

Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-18 15:32:45 +02:00
Alexander Graf 2a60dba43c kvm: Update kernel headers
Corresponding kvm.git hash: 4e3c8a1b1c

Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-18 15:32:45 +02:00
Alexander Graf 5f629d943c s390x: fix s390 virtio aliases
Some of the virtio devices have the same frontend name, but actually
implement different devices behind the scenes through aliases.

The indicator which device type to use is the architecture. On s390, we
want s390 virtio devices. On everything else, we want PCI devices.

Reflect this in the alias selection code. This way we fix commands like
-device virtio-blk on s390x which with this patch applied select the
correct virtio-blk-s390 device rather than virtio-blk-pci.

Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-18 15:32:45 +02:00
Paolo Bonzini 89bfe00043 qom: Push error reporting to object_property_find()
Avoids duplicated error_set().

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[AF: Also drop error_set() in object_property_del().]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18 15:14:38 +02:00
Paolo Bonzini 8cb6789a31 qdev: Remove qdev_prop_exists()
Can be replaced everywhere with object_property_find().

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18 15:14:38 +02:00
Anthony Liguori ac7d1ba6d1 qbus: Initialize in standard way
Move code to an initfn and finalizer.
Replace do_qbus_create_inplace() with qbus_realize().

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18 15:14:38 +02:00