Commit graph

42 commits

Author SHA1 Message Date
Richard Henderson 133b84c819 target-tilegx: Handle nofault prefetch instructions
These are mapped onto some of the normal load instructions, when the
destination is the zero register.  Other load insns do fault even
when targeting the zero register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:16 +11:00
Chen Gang 95df61e623 target-tilegx: Fix a typo for mnemonic about "ld_add"
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443562720-3008-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:16 +11:00
Richard Henderson a0577d2aa9 target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV
Consolidate signal handling under a single exception.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:15 +11:00
Chen Gang dd8070d865 target-tilegx: Decode ill pseudo-instructions
Notice raise and bpt, decoding the constants embedded in the
nop addil instruction in the x0 slot.

[rth: Generalize TILEGX_EXCP_OPCODE_ILL to TILEGX_EXCP_SIGNAL.
Drop validation of signal values.]

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443243635-4886-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:15 +11:00
Chen Gang f723287944 target-tilegx: Let x1 pipe process bpt instruction only
According to the related document, bpt can be only in x1 pipe.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:15 +11:00
Richard Henderson 9ff5b57c21 target-tilegx: Implement complex multiply instructions
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:14 +11:00
Richard Henderson 0b4232f108 target-tilegx: Implement table index instructions
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:14 +11:00
Richard Henderson ba1fc78f65 target-tilegx: Implement crc instructions
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:14 +11:00
Chen Gang 38c949ffe7 target-tilegx: Implement v1multu instruction
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:14 +11:00
Chen Gang c6876d7e1c target-tilegx: Implement v*add and v*sub instructions
[rth: Implement everything inline; handle v1addi and v2addi as well.]

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1442873918-3394-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:14 +11:00
Chen Gang 0ab0a3d768 target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
v2sh* are implemented with helper functions; v4sh* are implmeneted
with inline code.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:03:13 +11:00
Richard Henderson 0551301076 target-tilegx: Tidy simd_helper.c
Using the V1 macro when we want to replicate a byte across
the 8 elements of the word.  Using deposit and extract for
manipulating specific elements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:01:41 +11:00
Richard Henderson 461aa6783e target-tilegx: Handle v1shl, v1shru, v1shrs
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:34 -07:00
Richard Henderson 3be19e8c83 target-tilegx: Handle v1shli, v1shrui
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:34 -07:00
Richard Henderson 5151c69abc target-tilegx: Handle v4int_l/h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:34 -07:00
Richard Henderson 0583b23323 target-tilegx: Handle atomic instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:34 -07:00
Richard Henderson 03b217b168 target-tilegx: Handle mtspr, mfspr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson e7346cf036 target-tilegx: Handle v1cmpeq, v1cmpne
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 661ff7431f target-tilegx: Handle mask instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 4ff49775ec target-tilegx: Handle scalar multiply instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson f090f9f7ce target-tilegx: Handle conditional move instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 2369976deb target-tilegx: Handle shift instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson c06b181729 target-tilegx: Handle bitfield instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson d5dbd6eb38 target-tilegx: Implement system and memory management instructions
Most of which are either nops or exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 73c543776b target-tilegx: Handle comparison instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson e04e98bf27 target-tilegx: Handle conditional branch instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson c230a9944d target-tilegx: Handle unconditional jump instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 01cd675cfe target-tilegx: Handle post-increment load and store instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 0426335d4f target-tilegx: Handle basic load and store instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 7f41a8d672 target-tilegx: Handle most bit manipulation instructions
The crc instructions are omitted from this set.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson 89b8c7504f target-tilegx: Handle arithmetic instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:33 -07:00
Richard Henderson a9fdfc7e7b target-tilegx: Handle simple logical operations
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:32 -07:00
Chen Gang 444e06b172 target-tilegx: Add TILE-Gx building files
Add related configuration and make files for tilegx.
The target can now build, though not run anything.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP1588E5A03AD5E94B07E988B9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:32 -07:00
Richard Henderson 9b9dc7acec target-tilegx: Generate SEGV properly
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:28 -07:00
Richard Henderson 8fd29dd72b target-tilegx: Framework for decoding bundles
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:36 -07:00
Chen Gang 5b212be632 target-tilegx: Add several helpers for instructions translation
The related instructions are exception, cntlz, cnttz, shufflebytes.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <BLU436-SMTP83F96FD8422BE49AFDC9DFB9660@phx.gbl>
[rth: Remove incorrect implementation of add_saturate.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:36 -07:00
Chen Gang 9f64170df2 target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:36 -07:00
Chen Gang b69773a8a7 target-tilegx: Add special register information from Tilera Corporation
The related copy is from Linux kernel "arch/tile/include/uapi/arch/
spr_def_64.h".

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP1093D605AAE9B4837B564B8B9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:35 -07:00
Richard Henderson 4fe221820f target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
An obvious typo in the mnemonic here.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:35 -07:00
Richard Henderson c6c00e1722 target-tilegx: Modify _SPECIAL_ opcodes
Both ADDX_SPECIAL_0_OPCODE_Y1 and ADD_SPECIAL_0_OPCODE_Y1
do not appear to be "special" in any way, except that they
don't follow the normal naming convention using _RRR_.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:35 -07:00
Chen Gang 2c56c87fcf target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
"unsigned long long"

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP1945B04384351D5EE7D9DECB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:35 -07:00
Chen Gang b1406c6c59 target-tilegx: Add opcode basic implementation from Tilera Corporation
It is copied from Linux kernel "arch/tile/include/uapi/arch/
opcode_tilegx.h".

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP2087FA98B64A20B25155D9AB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:41:35 -07:00