acbbb94e57
If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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.. | ||
insn_trans | ||
cpu.c | ||
cpu.h | ||
cpu_bits.h | ||
cpu_helper.c | ||
cpu_user.h | ||
csr.c | ||
fpu_helper.c | ||
gdbstub.c | ||
helper.h | ||
insn16.decode | ||
insn32-64.decode | ||
insn32.decode | ||
instmap.h | ||
Makefile.objs | ||
op_helper.c | ||
pmp.c | ||
pmp.h | ||
translate.c |