qemu-patch-raspberry4/target/riscv
Michael Clark d26f5a4234
RISC-V: Change local interrupts from edge to level
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- https://github.com/riscv/riscv-qemu/issues/132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

  echo 1 > /sys/devices/system/cpu/cpu2/online
  echo 0 > /sys/devices/system/cpu/cpu2/online
  echo 1 > /sys/devices/system/cpu/cpu2/online

Reported-by: Atish Patra <atishp04@gmail.com>
Cc: Atish Patra <atishp04@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-19 05:14:39 -07:00
..
insn_trans target/riscv: Fix manually parsed 16 bit insn 2019-03-17 22:21:32 -07:00
cpu.c RISC-V: Add hooks to use the gdb xml files. 2019-03-19 05:13:24 -07:00
cpu.h RISC-V: linux-user support for RVE ABI 2019-03-19 05:14:39 -07:00
cpu_bits.h RISC-V: Fixes to CSR_* register macros. 2019-03-19 05:13:24 -07:00
cpu_helper.c RISC-V: Change local interrupts from edge to level 2019-03-19 05:14:39 -07:00
cpu_user.h RISC-V: linux-user support for RVE ABI 2019-03-19 05:14:39 -07:00
csr.c RISC-V: Allow interrupt controllers to claim interrupts 2019-03-19 05:14:39 -07:00
fpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
gdbstub.c RISC-V: Add hooks to use the gdb xml files. 2019-03-19 05:13:24 -07:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
insn16.decode target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-13 10:40:46 +01:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
insn32.decode target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 2019-03-13 10:40:50 +01:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-13 10:34:06 +01:00
op_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
pmp.c riscv: pmp: Log pmp access errors as guest errors 2019-03-19 05:14:38 -07:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c target/riscv: Remove decode_RV32_64G() 2019-03-13 10:40:50 +01:00