Add readback that SM bit is set enabled/disabled
On PDI disable/enable, add polling readback that it is set/cleared. Set 1 is delayed until the end of a frame which is currently processed, ET1100 datasheet. This aligns the code base with SCC behavior.feature/add_sm_disabled_enabled_readback
parent
56124c2348
commit
41438c4a33
22
soes/esc.c
22
soes/esc.c
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@ -162,6 +162,17 @@ void ESC_SMwritepdi (uint8_t n)
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ESC_write ((uint16_t)(ESCREG_SM0PDI + (n << 3)), &(sm->ActPDI), 1);
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ESC_write ((uint16_t)(ESCREG_SM0PDI + (n << 3)), &(sm->ActPDI), 1);
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}
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}
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/** Read ESC PDI control register 0x807(+ offset to SyncManager n) to ESCvar.SM[n] data.
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*
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* @param[in] n = Read from Sync Manager no. n
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*/
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void ESC_SMreadpdi (uint8_t n)
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{
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_ESCsm2* sm;
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sm = (_ESCsm2*)&ESCvar.SM[n];
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ESC_read ((uint16_t)(ESCREG_SM0PDI + (n << 3)), &(sm->ActPDI), 1);
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}
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/** Write 0 to Bit0 in SM PDI control register 0x807(+ offset to SyncManager n) to Activate the Sync Manager n.
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/** Write 0 to Bit0 in SM PDI control register 0x807(+ offset to SyncManager n) to Activate the Sync Manager n.
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*
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*
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* @param[in] n = Write to Sync Manager no. n
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* @param[in] n = Write to Sync Manager no. n
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@ -172,6 +183,11 @@ void ESC_SMenable (uint8_t n)
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sm = (_ESCsm2 *)&ESCvar.SM[n];
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sm = (_ESCsm2 *)&ESCvar.SM[n];
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sm->ActPDI &= (uint8_t)~ESCREG_SMENABLE_BIT;
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sm->ActPDI &= (uint8_t)~ESCREG_SMENABLE_BIT;
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ESC_SMwritepdi (n);
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ESC_SMwritepdi (n);
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/* Read back wait until enabled */
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do
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{
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ESC_SMreadpdi (n);
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} while ((sm->ActPDI & ESCREG_SMENABLE_BIT) == 1);
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}
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}
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/** Write 1 to Bit0 in SM PDI control register 0x807(+ offset to SyncManager n) to De-activte the Sync Manager n.
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/** Write 1 to Bit0 in SM PDI control register 0x807(+ offset to SyncManager n) to De-activte the Sync Manager n.
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*
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*
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@ -183,6 +199,11 @@ void ESC_SMdisable (uint8_t n)
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sm = (_ESCsm2 *)&ESCvar.SM[n];
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sm = (_ESCsm2 *)&ESCvar.SM[n];
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sm->ActPDI |= ESCREG_SMENABLE_BIT;
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sm->ActPDI |= ESCREG_SMENABLE_BIT;
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ESC_SMwritepdi (n);
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ESC_SMwritepdi (n);
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/* Read back wait until disabled */
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do
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{
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ESC_SMreadpdi (n);
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} while ((sm->ActPDI & ESCREG_SMENABLE_BIT) == 0);
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}
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}
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/** Read Configured Station Address register 0x010 assigned by the Master.
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/** Read Configured Station Address register 0x010 assigned by the Master.
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*
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*
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@ -321,7 +342,6 @@ uint8_t ESC_startmbx (uint8_t state)
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ESCvar.activemb0 = &ESCvar.mb[0];
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ESCvar.activemb0 = &ESCvar.mb[0];
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ESCvar.activemb1 = &ESCvar.mb[1];
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ESCvar.activemb1 = &ESCvar.mb[1];
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ESC_SMenable (0);
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ESC_SMenable (0);
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ESC_SMenable (1);
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ESC_SMenable (1);
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ESC_SMstatus (0);
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ESC_SMstatus (0);
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