2005-07-02 22:59:34 +02:00
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/*
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* PowerPC CPU initialization for qemu.
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2007-09-16 23:08:06 +02:00
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*
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2007-03-07 09:32:30 +01:00
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* Copyright (c) 2003-2007 Jocelyn Mayer
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2011-12-22 13:26:17 +01:00
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* Copyright 2011 Freescale Semiconductor, Inc.
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2005-07-02 22:59:34 +02:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-19 08:11:26 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2005-07-02 22:59:34 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2005-07-02 22:59:34 +02:00
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*/
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2021-05-07 13:55:51 +02:00
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#include "qemu/osdep.h"
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2019-04-17 21:18:04 +02:00
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#include "disas/dis-asm.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/gdbstub.h"
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2011-10-13 00:40:32 +02:00
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#include "kvm_ppc.h"
|
2012-12-17 18:20:04 +01:00
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#include "sysemu/arch_init.h"
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2013-01-23 18:20:38 +01:00
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#include "sysemu/cpus.h"
|
2017-01-10 11:59:55 +01:00
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#include "sysemu/hw_accel.h"
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2019-05-23 16:35:05 +02:00
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#include "sysemu/tcg.h"
|
2013-02-18 00:16:49 +01:00
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#include "cpu-models.h"
|
2013-03-13 01:40:33 +01:00
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#include "mmu-hash32.h"
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#include "mmu-hash64.h"
|
2013-08-05 21:40:44 +02:00
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#include "qemu/error-report.h"
|
2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
|
2019-04-17 21:17:57 +02:00
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#include "qemu/qemu-print.h"
|
2018-02-01 12:18:31 +01:00
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#include "qapi/error.h"
|
2018-02-01 12:18:43 +01:00
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#include "qapi/qmp/qnull.h"
|
2014-05-23 04:26:50 +02:00
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#include "qapi/visitor.h"
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#include "hw/qdev-properties.h"
|
2016-03-15 14:32:19 +01:00
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#include "hw/ppc/ppc.h"
|
2017-03-01 07:54:38 +01:00
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#include "mmu-book3s-v3.h"
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2017-08-30 15:24:33 +02:00
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#include "qemu/cutils.h"
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2017-09-14 19:38:40 +02:00
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#include "disas/capstone.h"
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2018-01-19 19:24:22 +01:00
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#include "fpu/softfloat.h"
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2019-06-19 22:10:45 +02:00
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#include "qapi/qapi-commands-machine-target.h"
|
2007-09-29 14:01:46 +02:00
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2021-05-07 13:55:51 +02:00
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#include "exec/helper-proto.h"
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#include "helper_regs.h"
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#include "internal.h"
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#include "spr_tcg.h"
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2019-03-21 12:45:46 +01:00
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/* #define PPC_DEBUG_SPR */
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2014-06-23 15:23:08 +02:00
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/* #define USE_APPLE_GDB */
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2005-07-02 22:59:34 +02:00
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2017-04-20 03:05:26 +02:00
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static inline void vscr_init(CPUPPCState *env, uint32_t val)
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2009-02-03 20:55:59 +01:00
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{
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/* Altivec always uses round-to-nearest */
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set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
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2021-05-12 16:08:03 +02:00
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ppc_store_vscr(env, val);
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2009-02-03 20:55:59 +01:00
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}
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2021-05-01 04:29:22 +02:00
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/**
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* _spr_register
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*
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* Register an SPR with all the callbacks required for tcg,
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* and the ID number for KVM.
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*
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* The reason for the conditional compilation is that the tcg functions
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* may be compiled out, and the system kvm header may not be available
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* for supplying the ID numbers. This is ugly, but the best we can do.
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*/
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#ifdef CONFIG_TCG
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# define USR_ARG(X) X,
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# ifdef CONFIG_USER_ONLY
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# define SYS_ARG(X)
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# else
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# define SYS_ARG(X) X,
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# endif
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2007-03-07 09:32:30 +01:00
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#else
|
2021-05-01 04:29:22 +02:00
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# define USR_ARG(X)
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# define SYS_ARG(X)
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2013-02-20 17:41:50 +01:00
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#endif
|
2021-05-01 04:29:22 +02:00
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#ifdef CONFIG_KVM
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# define KVM_ARG(X) X,
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#else
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# define KVM_ARG(X)
|
2013-02-20 17:41:50 +01:00
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#endif
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2021-05-01 04:29:22 +02:00
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typedef void spr_callback(DisasContext *, int, int);
|
2013-02-20 17:41:50 +01:00
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2021-05-01 04:29:22 +02:00
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static void _spr_register(CPUPPCState *env, int num, const char *name,
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USR_ARG(spr_callback *uea_read)
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USR_ARG(spr_callback *uea_write)
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SYS_ARG(spr_callback *oea_read)
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SYS_ARG(spr_callback *oea_write)
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SYS_ARG(spr_callback *hea_read)
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SYS_ARG(spr_callback *hea_write)
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KVM_ARG(uint64_t one_reg_id)
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target_ulong initial_value)
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2005-07-02 22:59:34 +02:00
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{
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2021-05-01 04:29:22 +02:00
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ppc_spr_t *spr = &env->spr_cb[num];
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/* No SPR should be registered twice. */
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assert(spr->name == NULL);
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assert(name != NULL);
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2005-07-02 22:59:34 +02:00
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spr->name = name;
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2021-05-01 04:29:22 +02:00
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spr->default_value = initial_value;
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env->spr[num] = initial_value;
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#ifdef CONFIG_TCG
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2005-07-02 22:59:34 +02:00
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spr->uea_read = uea_read;
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spr->uea_write = uea_write;
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2021-05-01 04:29:22 +02:00
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# ifndef CONFIG_USER_ONLY
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2005-07-02 22:59:34 +02:00
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spr->oea_read = oea_read;
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spr->oea_write = oea_write;
|
2016-03-21 13:52:32 +01:00
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spr->hea_read = hea_read;
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spr->hea_write = hea_write;
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2021-05-01 04:29:22 +02:00
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# endif
|
2014-01-06 06:36:40 +01:00
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#endif
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2021-05-01 04:29:22 +02:00
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#ifdef CONFIG_KVM
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spr->one_reg_id = one_reg_id;
|
2007-03-07 09:32:30 +01:00
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#endif
|
2005-07-02 22:59:34 +02:00
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}
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2021-05-01 04:29:22 +02:00
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/* spr_register_kvm_hv passes all required arguments. */
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#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, hea_read, hea_write, \
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one_reg_id, initial_value) \
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_spr_register(env, num, name, \
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USR_ARG(uea_read) USR_ARG(uea_write) \
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SYS_ARG(oea_read) SYS_ARG(oea_write) \
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SYS_ARG(hea_read) SYS_ARG(hea_write) \
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KVM_ARG(one_reg_id) initial_value)
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/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
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#define spr_register_kvm(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, one_reg_id, ival) \
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spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
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oea_write, oea_read, oea_write, one_reg_id, ival)
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/* spr_register_hv and spr_register are similar, except there is no kvm id. */
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#define spr_register_hv(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, hea_read, hea_write, ival) \
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spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
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oea_write, hea_read, hea_write, 0, ival)
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#define spr_register(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, ival) \
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spr_register_kvm(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, 0, ival)
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|
2005-07-02 22:59:34 +02:00
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/* Generic PowerPC SPRs */
|
2021-05-05 17:53:07 +02:00
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static void register_generic_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
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{
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/* Integer processing */
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spr_register(env, SPR_XER, "XER",
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&spr_read_xer, &spr_write_xer,
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&spr_read_xer, &spr_write_xer,
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0x00000000);
|
2020-10-09 08:44:37 +02:00
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/* Branch control */
|
2005-07-02 22:59:34 +02:00
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spr_register(env, SPR_LR, "LR",
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&spr_read_lr, &spr_write_lr,
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&spr_read_lr, &spr_write_lr,
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0x00000000);
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spr_register(env, SPR_CTR, "CTR",
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&spr_read_ctr, &spr_write_ctr,
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&spr_read_ctr, &spr_write_ctr,
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0x00000000);
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/* Interrupt processing */
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spr_register(env, SPR_SRR0, "SRR0",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_SRR1, "SRR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Processor control */
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spr_register(env, SPR_SPRG0, "SPRG0",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_SPRG1, "SPRG1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_SPRG2, "SPRG2",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_SPRG3, "SPRG3",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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}
|
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/* SPR common to all non-embedded PowerPC, including 601 */
|
2021-05-05 17:53:07 +02:00
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static void register_ne_601_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
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{
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/* Exception processing */
|
2013-02-20 17:41:50 +01:00
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spr_register_kvm(env, SPR_DSISR, "DSISR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_DSISR, 0x00000000);
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spr_register_kvm(env, SPR_DAR, "DAR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_DAR, 0x00000000);
|
2005-07-02 22:59:34 +02:00
|
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/* Timer */
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spr_register(env, SPR_DECR, "DECR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_decr, &spr_write_decr,
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0x00000000);
|
2017-03-01 07:54:37 +01:00
|
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}
|
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/* Storage Description Register 1 */
|
2021-05-05 17:53:07 +02:00
|
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static void register_sdr1_sprs(CPUPPCState *env)
|
2017-03-01 07:54:37 +01:00
|
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|
{
|
2017-02-20 00:54:48 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
if (env->has_hv_mode) {
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* SDR1 is a hypervisor resource on CPUs which have a
|
|
|
|
* hypervisor mode
|
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*/
|
2017-02-20 00:54:48 +01:00
|
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spr_register_hv(env, SPR_SDR1, "SDR1",
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SPR_NOACCESS, SPR_NOACCESS,
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|
SPR_NOACCESS, SPR_NOACCESS,
|
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&spr_read_generic, &spr_write_sdr1,
|
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|
0x00000000);
|
|
|
|
} else {
|
|
|
|
spr_register(env, SPR_SDR1, "SDR1",
|
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|
|
SPR_NOACCESS, SPR_NOACCESS,
|
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|
|
&spr_read_generic, &spr_write_sdr1,
|
|
|
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0x00000000);
|
|
|
|
}
|
|
|
|
#endif
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* BATs 0-3 */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_low_BATs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-07-02 22:59:34 +02:00
|
|
|
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT0U, "DBAT0U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_BATs += 4;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* BATs 4-7 */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_high_BATs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-07-02 22:59:34 +02:00
|
|
|
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_BATs += 4;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Generic PowerPC time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_tbl(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_VTBL, "TBL",
|
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_TBL, "TBL",
|
2010-03-26 01:25:36 +01:00
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
&spr_read_tbl, &spr_write_tbl,
|
2005-07-02 22:59:34 +02:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_VTBU, "TBU",
|
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_TBU, "TBU",
|
2010-03-26 01:25:36 +01:00
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
&spr_read_tbu, &spr_write_tbu,
|
2005-07-02 22:59:34 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Softare table search registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-03-07 09:32:30 +01:00
|
|
|
env->nb_tlb = nb_tlbs;
|
|
|
|
env->nb_ways = nb_ways;
|
|
|
|
env->id_tlbs = 1;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_6XX;
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_DMISS, "DMISS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DCMP, "DCMP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_HASH1, "HASH1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_HASH2, "HASH2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IMISS, "IMISS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_ICMP, "ICMP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_RPA, "RPA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR common to MPC755 and G2 */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_G2_755_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* SGPRs */
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2005-07-02 22:59:34 +02:00
|
|
|
/* SPR common to all 7xx PowerPC implementations */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_7xx_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
/* Breakpoints */
|
|
|
|
/* XXX : not implemented */
|
2013-02-20 17:41:50 +01:00
|
|
|
spr_register_kvm(env, SPR_DABR, "DABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DABR, 0x00000000);
|
2005-07-02 22:59:34 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Cache management */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTC, "ICTC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Performance monitors */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC1, "PMC1",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC2, "PMC2",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC3, "PMC3",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC4, "PMC4",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_SIAR, "SIAR",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC1, "UPMC1",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC2, "UPMC2",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC3, "UPMC3",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC4, "UPMC4",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_USIAR, "USIAR",
|
2005-07-02 22:59:34 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* External access control */
|
2005-07-02 22:59:34 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-03-12 01:31:47 +01:00
|
|
|
#ifdef TARGET_PPC64
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_amr_sprs(CPUPPCState *env)
|
2013-03-12 01:31:47 +01:00
|
|
|
{
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* Virtual Page Class Key protection
|
|
|
|
*
|
|
|
|
* The AMR is accessible either via SPR 13 or SPR 29. 13 is
|
2013-03-12 01:31:47 +01:00
|
|
|
* userspace accessible, 29 is privileged. So we only need to set
|
2019-03-21 12:45:46 +01:00
|
|
|
* the kvm ONE_REG id on one of them, we use 29
|
|
|
|
*/
|
2013-03-12 01:31:47 +01:00
|
|
|
spr_register(env, SPR_UAMR, "UAMR",
|
2016-03-21 13:52:37 +01:00
|
|
|
&spr_read_generic, &spr_write_amr,
|
|
|
|
&spr_read_generic, &spr_write_amr,
|
2013-03-12 01:31:47 +01:00
|
|
|
0);
|
2016-03-21 13:52:37 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_AMR, "AMR",
|
2013-03-12 01:31:47 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2016-03-21 13:52:37 +01:00
|
|
|
&spr_read_generic, &spr_write_amr,
|
2013-03-12 01:31:47 +01:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
2014-01-06 06:36:39 +01:00
|
|
|
KVM_REG_PPC_AMR, 0);
|
2016-03-21 13:52:37 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
|
2013-03-12 01:31:47 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2016-03-21 13:52:37 +01:00
|
|
|
&spr_read_generic, &spr_write_uamor,
|
2013-03-12 01:31:47 +01:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_UAMOR, 0);
|
2016-03-21 13:52:33 +01:00
|
|
|
spr_register_hv(env, SPR_AMOR, "AMOR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0);
|
2017-03-01 07:54:37 +01:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_iamr_sprs(CPUPPCState *env)
|
2017-03-01 07:54:37 +01:00
|
|
|
{
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_iamr,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_IAMR, 0);
|
2013-03-12 01:31:47 +01:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
}
|
|
|
|
#endif /* TARGET_PPC64 */
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_thrm_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
/* Thermal management */
|
2005-07-02 22:59:34 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_THRM1, "THRM1",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2016-06-20 03:27:14 +02:00
|
|
|
&spr_read_thrm, &spr_write_generic,
|
2005-07-02 22:59:34 +02:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_THRM2, "THRM2",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2016-06-20 03:27:14 +02:00
|
|
|
&spr_read_thrm, &spr_write_generic,
|
2005-07-02 22:59:34 +02:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_THRM3, "THRM3",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2016-06-20 03:27:14 +02:00
|
|
|
&spr_read_thrm, &spr_write_generic,
|
2005-07-02 22:59:34 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR specific to PowerPC 604 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_604_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* Breakpoints */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2013-02-20 17:41:50 +01:00
|
|
|
spr_register_kvm(env, SPR_DABR, "DABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DABR, 0x00000000);
|
2005-07-02 22:59:34 +02:00
|
|
|
/* Performance counters */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC1, "PMC1",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC2, "PMC2",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_SIAR, "SIAR",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_SDA, "SDA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* External access control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* SPR specific to PowerPC 603 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_603_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
/* External access control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
2005-07-02 22:59:34 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-03-07 09:32:30 +01:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2013-04-03 06:03:38 +02:00
|
|
|
/* Breakpoints */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* SPR specific to PowerPC G2 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_G2_sprs(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Memory base address */
|
|
|
|
/* MBAR */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_MBAR, "MBAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Exception processing */
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Breakpoints */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DABR, "DABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DABR2, "DABR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR2, "IABR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IBCR, "IBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DBCR, "DBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR specific to PowerPC 602 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_602_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* ESA registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_SER, "SER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_SEBR, "SEBR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_ESASRR, "ESASRR",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Floating point status */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_SP, "SP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LT, "LT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Watchdog timer */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_TCR, "TCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Interrupt base */
|
|
|
|
spr_register(env, SPR_IBR, "IBR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR specific to PowerPC 601 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_601_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* Multiplication/division register */
|
|
|
|
/* MQ */
|
|
|
|
spr_register(env, SPR_MQ, "MQ",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* RTC registers */
|
|
|
|
spr_register(env, SPR_601_RTCU, "RTCU",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_601_rtcu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_601_VRTCU, "RTCU",
|
|
|
|
&spr_read_601_rtcu, SPR_NOACCESS,
|
|
|
|
&spr_read_601_rtcu, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_601_RTCL, "RTCL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_601_rtcl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_601_VRTCL, "RTCL",
|
|
|
|
&spr_read_601_rtcl, SPR_NOACCESS,
|
|
|
|
&spr_read_601_rtcl, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Timer */
|
|
|
|
#if 0 /* ? */
|
|
|
|
spr_register(env, SPR_601_UDECR, "UDECR",
|
|
|
|
&spr_read_decr, SPR_NOACCESS,
|
|
|
|
&spr_read_decr, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
#endif
|
|
|
|
/* External access control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_601_ubat, &spr_write_601_ubatl,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_BATs = 4;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_74xx_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_74XX_MMCR2, "MMCR2",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX: not implemented */
|
|
|
|
spr_register(env, SPR_BAMR, "BAMR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_MSSCR0, "MSSCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Altivec */
|
|
|
|
spr_register(env, SPR_VRSAVE, "VRSAVE",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_l3_ctrl(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
/* L3CR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3CR, "L3CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3ITCR0 */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_L3ITCR0, "L3ITCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3PM */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_L3PM, "L3PM",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-10-01 06:48:45 +02:00
|
|
|
env->nb_tlb = nb_tlbs;
|
|
|
|
env->nb_ways = nb_ways;
|
|
|
|
env->id_tlbs = 1;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_6XX;
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_PTEHI, "PTEHI",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_PTELO, "PTELO",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_TLBMISS, "TLBMISS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_usprg3_sprs(CPUPPCState *env)
|
2017-04-19 18:48:22 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_USPRG3, "USPRG3",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_usprgh_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* PowerPC BookE SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
2008-09-20 10:07:15 +02:00
|
|
|
const char *ivor_names[64] = {
|
2007-11-18 00:02:20 +01:00
|
|
|
"IVOR0", "IVOR1", "IVOR2", "IVOR3",
|
|
|
|
"IVOR4", "IVOR5", "IVOR6", "IVOR7",
|
|
|
|
"IVOR8", "IVOR9", "IVOR10", "IVOR11",
|
|
|
|
"IVOR12", "IVOR13", "IVOR14", "IVOR15",
|
|
|
|
"IVOR16", "IVOR17", "IVOR18", "IVOR19",
|
|
|
|
"IVOR20", "IVOR21", "IVOR22", "IVOR23",
|
|
|
|
"IVOR24", "IVOR25", "IVOR26", "IVOR27",
|
|
|
|
"IVOR28", "IVOR29", "IVOR30", "IVOR31",
|
|
|
|
"IVOR32", "IVOR33", "IVOR34", "IVOR35",
|
|
|
|
"IVOR36", "IVOR37", "IVOR38", "IVOR39",
|
|
|
|
"IVOR40", "IVOR41", "IVOR42", "IVOR43",
|
|
|
|
"IVOR44", "IVOR45", "IVOR46", "IVOR47",
|
|
|
|
"IVOR48", "IVOR49", "IVOR50", "IVOR51",
|
|
|
|
"IVOR52", "IVOR53", "IVOR54", "IVOR55",
|
|
|
|
"IVOR56", "IVOR57", "IVOR58", "IVOR59",
|
|
|
|
"IVOR60", "IVOR61", "IVOR62", "IVOR63",
|
|
|
|
};
|
|
|
|
#define SPR_BOOKE_IVORxx (-1)
|
|
|
|
int ivor_sprn[64] = {
|
|
|
|
SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
|
|
|
|
SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
|
|
|
|
SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
|
|
|
|
SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
|
2012-01-19 19:31:51 +01:00
|
|
|
SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
|
|
|
|
SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
|
2007-11-18 00:02:20 +01:00
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Interrupt processing */
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Debug */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2012-10-06 22:54:25 +02:00
|
|
|
&spr_read_generic, &spr_write_40x_dbcr0,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2018-08-14 18:09:51 +02:00
|
|
|
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-16 22:09:45 +02:00
|
|
|
&spr_read_generic, &spr_write_clear,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_DEAR, "DEAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_ESR, "ESR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-10-01 03:32:49 +02:00
|
|
|
&spr_read_generic, &spr_write_excp_prefix,
|
2007-03-30 12:07:33 +02:00
|
|
|
0x00000000);
|
|
|
|
/* Exception vectors */
|
2007-11-18 00:02:20 +01:00
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
if (ivor_mask & (1ULL << i)) {
|
|
|
|
if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
|
|
|
|
fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
spr_register(env, ivor_sprn[i], ivor_names[i],
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_excp_vector,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_BOOKE_PID, "PID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
&spr_read_generic, &spr_write_booke_pid,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_TCR, "TCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_booke_tcr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_TSR, "TSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_booke_tsr,
|
|
|
|
0x00000000);
|
|
|
|
/* Timer */
|
|
|
|
spr_register(env, SPR_DECR, "DECR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_decr, &spr_write_decr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_DECAR, "DECAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRGs */
|
|
|
|
spr_register(env, SPR_USPRG0, "USPRG0",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2018-08-14 18:09:51 +02:00
|
|
|
spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
2021-05-07 13:55:51 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2021-05-05 17:53:07 +02:00
|
|
|
static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
|
2011-04-30 23:34:58 +02:00
|
|
|
uint32_t maxsize, uint32_t flags,
|
|
|
|
uint32_t nentries)
|
|
|
|
{
|
|
|
|
return (assoc << TLBnCFG_ASSOC_SHIFT) |
|
|
|
|
(minsize << TLBnCFG_MINSIZE_SHIFT) |
|
|
|
|
(maxsize << TLBnCFG_MAXSIZE_SHIFT) |
|
|
|
|
flags | nentries;
|
|
|
|
}
|
2021-05-07 13:55:51 +02:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
2011-04-30 23:34:58 +02:00
|
|
|
|
|
|
|
/* BookE 2.06 storage control registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
|
2017-08-07 17:50:47 +02:00
|
|
|
uint32_t *tlbncfg, uint32_t mmucfg)
|
2007-03-30 12:07:33 +02:00
|
|
|
{
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2008-09-20 10:07:15 +02:00
|
|
|
const char *mas_names[8] = {
|
2007-11-18 00:02:20 +01:00
|
|
|
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
|
|
|
|
};
|
|
|
|
int mas_sprn[8] = {
|
|
|
|
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
|
|
|
|
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
2007-03-30 12:07:33 +02:00
|
|
|
/* TLB assist registers */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
for (i = 0; i < 8; i++) {
|
2019-03-21 12:45:46 +01:00
|
|
|
void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
|
|
|
|
&spr_write_generic32;
|
2012-06-21 14:01:06 +02:00
|
|
|
if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
|
|
|
|
uea_write = &spr_write_generic;
|
|
|
|
}
|
2007-11-18 00:02:20 +01:00
|
|
|
if (mas_mask & (1 << i)) {
|
|
|
|
spr_register(env, mas_sprn[i], mas_names[i],
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2012-06-21 14:01:06 +02:00
|
|
|
&spr_read_generic, uea_write,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
}
|
2007-03-30 12:07:33 +02:00
|
|
|
if (env->nb_pids > 1) {
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_PID1, "PID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
&spr_read_generic, &spr_write_booke_pid,
|
2007-03-30 12:07:33 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
if (env->nb_pids > 2) {
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-03-30 12:07:33 +02:00
|
|
|
spr_register(env, SPR_BOOKE_PID2, "PID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
&spr_read_generic, &spr_write_booke_pid,
|
2007-03-30 12:07:33 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
2018-09-21 08:59:07 +02:00
|
|
|
|
|
|
|
spr_register(env, SPR_BOOKE_EPLC, "EPLC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_eplc,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_EPSC, "EPSC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_epsc,
|
|
|
|
0x00000000);
|
|
|
|
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-10-05 15:11:25 +02:00
|
|
|
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
2007-03-30 12:07:33 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2017-08-07 17:50:47 +02:00
|
|
|
mmucfg);
|
2007-03-30 12:07:33 +02:00
|
|
|
switch (env->nb_ways) {
|
|
|
|
case 4:
|
|
|
|
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
tlbncfg[3]);
|
2007-03-30 12:07:33 +02:00
|
|
|
/* Fallthru */
|
|
|
|
case 3:
|
|
|
|
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
tlbncfg[2]);
|
2007-03-30 12:07:33 +02:00
|
|
|
/* Fallthru */
|
|
|
|
case 2:
|
|
|
|
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
tlbncfg[1]);
|
2007-03-30 12:07:33 +02:00
|
|
|
/* Fallthru */
|
|
|
|
case 1:
|
|
|
|
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
tlbncfg[0]);
|
2007-03-30 12:07:33 +02:00
|
|
|
/* Fallthru */
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2011-04-30 23:34:58 +02:00
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
register_usprgh_sprs(env);
|
2007-03-30 12:07:33 +02:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* SPR specific to PowerPC 440 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_440_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* Cache control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DNV0, "DNV0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DNV1, "DNV1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DNV2, "DNV2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DNV3, "DNV3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_DTV0, "DTV0",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_DTV1, "DTV1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_DTV2, "DTV2",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_DTV3, "DTV3",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DVLIM, "DVLIM",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_INV0, "INV0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_INV1, "INV1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_INV2, "INV2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_INV3, "INV3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_ITV0, "ITV0",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_ITV1, "ITV1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_ITV2, "ITV2",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_440_ITV3, "ITV3",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_IVLIM, "IVLIM",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Cache debug */
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_DBDR, "DBDR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Processor control */
|
|
|
|
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_440_RSTCFG, "RSTCFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Storage control */
|
|
|
|
spr_register(env, SPR_440_MMUCR, "MMUCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR shared between PowerPC 40x implementations */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_40x_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* Cache */
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_40x_DCCR, "DCCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_40x_ICCR, "ICCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Exception */
|
|
|
|
spr_register(env, SPR_40x_DEAR, "DEAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_ESR, "ESR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_EVPR, "EVPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-10-01 03:32:49 +02:00
|
|
|
&spr_read_generic, &spr_write_excp_prefix,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_SRR2, "SRR2",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_SRR3, "SRR3",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Timers */
|
|
|
|
spr_register(env, SPR_40x_PIT, "PIT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_40x_pit, &spr_write_40x_pit,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_TCR, "TCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_booke_tcr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_TSR, "TSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_booke_tsr,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR specific to PowerPC 405 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_405_sprs(CPUPPCState *env)
|
2007-09-21 07:50:37 +02:00
|
|
|
{
|
|
|
|
/* MMU */
|
|
|
|
spr_register(env, SPR_40x_PID, "PID",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-09-21 07:50:37 +02:00
|
|
|
0x00700000);
|
|
|
|
/* Debug interface */
|
2007-03-07 09:32:30 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-16 22:09:45 +02:00
|
|
|
&spr_read_generic, &spr_write_40x_dbcr0,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_405_DBCR1, "DBCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_40x_DBSR, "DBSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-16 22:09:45 +02:00
|
|
|
&spr_read_generic, &spr_write_clear,
|
|
|
|
/* Last reset was system reset */
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000300);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_DAC1, "DAC1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_DAC2, "DAC2",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_405_DVC1, "DVC1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-09-21 07:50:37 +02:00
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_405_DVC2, "DVC2",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_IAC1, "IAC1",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_IAC2, "IAC2",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_405_IAC3, "IAC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_405_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Storage control */
|
2007-10-01 03:38:03 +02:00
|
|
|
/* XXX: TODO: not implemented */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_405_SLER, "SLER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-24 08:44:14 +02:00
|
|
|
&spr_read_generic, &spr_write_40x_sler,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_ZPR, "ZPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-03-07 09:32:30 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_405_SU0R, "SU0R",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRG */
|
|
|
|
spr_register(env, SPR_USPRG0, "USPRG0",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-17 04:50:56 +02:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-17 04:50:56 +02:00
|
|
|
spr_read_generic, &spr_write_generic,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-17 04:50:56 +02:00
|
|
|
spr_read_generic, &spr_write_generic,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-04-17 04:50:56 +02:00
|
|
|
spr_read_generic, &spr_write_generic,
|
2007-03-07 09:32:30 +01:00
|
|
|
0x00000000);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_usprgh_sprs(env);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR shared between PowerPC 401 & 403 implementations */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_401_403_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
|
|
|
spr_register(env, SPR_403_VTBL, "TBL",
|
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_TBL, "TBL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_VTBU, "TBU",
|
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_TBU, "TBU",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbu,
|
|
|
|
0x00000000);
|
|
|
|
/* Debug */
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_403_CDBCR, "CDBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2007-09-21 07:50:37 +02:00
|
|
|
/* SPR specific to PowerPC 401 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_401_sprs(CPUPPCState *env)
|
2007-09-21 07:50:37 +02:00
|
|
|
{
|
|
|
|
/* Debug interface */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DBCR0, "DBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_40x_dbcr0,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DBSR, "DBSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_clear,
|
|
|
|
/* Last reset was system reset */
|
|
|
|
0x00000300);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DAC1, "DAC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_IAC1, "IAC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Storage control */
|
2007-10-01 03:38:03 +02:00
|
|
|
/* XXX: TODO: not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_405_SLER, "SLER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_40x_sler,
|
|
|
|
0x00000000);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU never does speculative access */
|
2007-10-01 03:38:03 +02:00
|
|
|
spr_register(env, SPR_40x_SGR, "SGR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0xFFFFFFFF);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-10-01 03:38:03 +02:00
|
|
|
spr_register(env, SPR_40x_DCWR, "DCWR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_401x2_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_401_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_40x_PID, "PID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_40x_ZPR, "ZPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* SPR specific to PowerPC 403 implementation */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_403_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-09-21 07:50:37 +02:00
|
|
|
/* Debug interface */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_40x_dbcr0,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DBSR, "DBSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_clear,
|
|
|
|
/* Last reset was system reset */
|
|
|
|
0x00000300);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_DAC1, "DAC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_DAC2, "DAC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_40x_IAC1, "IAC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_IAC2, "IAC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_403_real_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_403_PBL1, "PBL1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_403_pbr, &spr_write_403_pbr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_PBU1, "PBU1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_403_pbr, &spr_write_403_pbr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_PBL2, "PBL2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_403_pbr, &spr_write_403_pbr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_403_PBU2, "PBU2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_403_pbr, &spr_write_403_pbr,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_403_mmu_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
/* MMU */
|
|
|
|
spr_register(env, SPR_40x_PID, "PID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-09-21 07:50:37 +02:00
|
|
|
spr_register(env, SPR_40x_ZPR, "ZPR",
|
2007-03-07 09:32:30 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SPR specific to PowerPC compression coprocessor extension */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_compress_sprs(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-03-07 09:32:30 +01:00
|
|
|
spr_register(env, SPR_401_SKR, "SKR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_5xx_8xx_sprs(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Exception processing */
|
2013-02-20 17:41:50 +01:00
|
|
|
spr_register_kvm(env, SPR_DSISR, "DSISR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DSISR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_DAR, "DAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DAR, 0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Timer */
|
|
|
|
spr_register(env, SPR_DECR, "DECR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_decr, &spr_write_decr,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_EIE, "EIE",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_EID, "EID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_NRI, "NRI",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPA, "CMPA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPB, "CMPB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPC, "CMPC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPD, "CMPD",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_ECR, "ECR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_DER, "DER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_COUNTA, "COUNTA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_COUNTB, "COUNTB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPE, "CMPE",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPF, "CMPF",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPG, "CMPG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_CMPH, "CMPH",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_BAR, "BAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_DPDR, "DPDR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_IMMR, "IMMR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_5xx_sprs(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_RCPU_FPECR, "FPECR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_8xx_sprs(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_DC_CST, "DC_CST",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_AP, "MI_AP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_AP, "MD_AP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_TW, "MD_TW",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* AMR => SPR 29 (Power 2.04)
|
|
|
|
* CTRL => SPR 136 (Power 2.04)
|
|
|
|
* CTRL => SPR 152 (Power 2.04)
|
|
|
|
* SCOMC => SPR 276 (64 bits ?)
|
|
|
|
* SCOMD => SPR 277 (64 bits ?)
|
|
|
|
* TBU40 => SPR 286 (Power 2.04 hypv)
|
|
|
|
* HSPRG0 => SPR 304 (Power 2.04 hypv)
|
|
|
|
* HSPRG1 => SPR 305 (Power 2.04 hypv)
|
|
|
|
* HDSISR => SPR 306 (Power 2.04 hypv)
|
|
|
|
* HDAR => SPR 307 (Power 2.04 hypv)
|
|
|
|
* PURR => SPR 309 (Power 2.04 hypv)
|
|
|
|
* HDEC => SPR 310 (Power 2.04 hypv)
|
|
|
|
* HIOR => SPR 311 (hypv)
|
|
|
|
* RMOR => SPR 312 (970)
|
|
|
|
* HRMOR => SPR 313 (Power 2.04 hypv)
|
|
|
|
* HSRR0 => SPR 314 (Power 2.04 hypv)
|
|
|
|
* HSRR1 => SPR 315 (Power 2.04 hypv)
|
|
|
|
* LPIDR => SPR 317 (970)
|
|
|
|
* EPR => SPR 702 (Power 2.04 emb)
|
|
|
|
* perf => 768-783 (Power 2.04)
|
|
|
|
* perf => 784-799 (Power 2.04)
|
|
|
|
* PPR => SPR 896 (Power 2.04)
|
|
|
|
* DABRX => 1015 (Power 2.04 hypv)
|
|
|
|
* FPECR => SPR 1022 (?)
|
|
|
|
* ... and more (thermal management, performance counters, ...)
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
/* Exception vectors models */
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_4xx_real(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
|
|
|
|
env->ivor_mask = 0x0000FFF0UL;
|
2007-11-03 14:37:12 +01:00
|
|
|
env->ivpr_mask = 0xFFFF0000UL;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0xFFFFFFFCUL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_4xx_softmmu(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
|
|
|
|
env->ivor_mask = 0x0000FFF0UL;
|
|
|
|
env->ivpr_mask = 0xFFFF0000UL;
|
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0xFFFFFFFCUL;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_MPC5xx(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
|
|
|
|
env->ivor_mask = 0x0000FFF0UL;
|
|
|
|
env->ivpr_mask = 0xFFFF0000UL;
|
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_MPC8xx(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2007-11-18 00:02:20 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2007-11-18 00:02:20 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
|
|
|
|
env->ivor_mask = 0x0000FFF0UL;
|
|
|
|
env->ivpr_mask = 0xFFFF0000UL;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_G2(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2007-11-18 00:02:20 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2012-06-21 15:17:59 +02:00
|
|
|
static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
|
|
|
|
env->ivor_mask = 0x0000FFF7UL;
|
2012-06-21 15:17:59 +02:00
|
|
|
env->ivpr_mask = ivpr_mask;
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0xFFFFFFFCUL;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_BookE(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
|
2014-09-05 18:39:05 +02:00
|
|
|
env->ivor_mask = 0x0000FFF0UL;
|
2007-11-18 00:02:20 +01:00
|
|
|
env->ivpr_mask = 0xFFFF0000UL;
|
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0xFFFFFFFCUL;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_601(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
2007-11-18 00:02:20 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_602(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-11-19 14:22:47 +01:00
|
|
|
/* XXX: exception prefix has a special behavior on 602 */
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-11-18 00:02:20 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_603(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_604(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
2009-04-28 20:07:01 +02:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_7x0(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2007-11-21 14:08:23 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_750cl(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-11-21 14:08:23 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_750cx(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2007-10-08 04:23:00 +02:00
|
|
|
/* XXX: Check if this is correct */
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_7x5(CPUPPCState *env)
|
2007-10-08 04:23:00 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2007-11-21 14:08:23 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
2007-10-08 04:23:00 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2007-11-21 14:08:23 +01:00
|
|
|
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
2007-10-08 04:23:00 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-10-08 04:23:00 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_7400(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_7450(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-29 03:06:28 +01:00
|
|
|
env->hreset_vector = 0x00000100UL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
static void init_excp_970(CPUPPCState *env)
|
2007-09-29 15:06:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
|
2007-10-05 15:09:54 +02:00
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0x0000000000000100ULL;
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
}
|
2011-04-01 06:15:19 +02:00
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_excp_POWER7(CPUPPCState *env)
|
2011-04-01 06:15:19 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2016-06-21 23:48:49 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
|
2011-04-01 06:15:19 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
2013-10-22 13:06:17 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
|
2011-04-01 06:15:19 +02:00
|
|
|
/* Hardware reset vector */
|
|
|
|
env->hreset_vector = 0x0000000000000100ULL;
|
|
|
|
#endif
|
|
|
|
}
|
2016-06-21 23:48:49 +02:00
|
|
|
|
|
|
|
static void init_excp_POWER8(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_excp_POWER7(env);
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
|
|
|
|
env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2019-02-15 17:16:46 +01:00
|
|
|
static void init_excp_POWER9(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_excp_POWER8(env);
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
|
2021-05-01 09:24:34 +02:00
|
|
|
env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
|
2019-02-15 17:16:46 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2019-12-05 19:44:50 +01:00
|
|
|
static void init_excp_POWER10(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_excp_POWER9(env);
|
|
|
|
}
|
|
|
|
|
2007-09-29 15:06:16 +02:00
|
|
|
#endif
|
|
|
|
|
2007-10-26 01:14:50 +02:00
|
|
|
/*****************************************************************************/
|
|
|
|
/* Power management enable checks */
|
2017-04-20 03:05:26 +02:00
|
|
|
static int check_pow_none(CPUPPCState *env)
|
2007-10-26 01:14:50 +02:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static int check_pow_nocheck(CPUPPCState *env)
|
2007-10-26 01:14:50 +02:00
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static int check_pow_hid0(CPUPPCState *env)
|
2007-10-26 01:14:50 +02:00
|
|
|
{
|
2019-03-21 12:45:46 +01:00
|
|
|
if (env->spr[SPR_HID0] & 0x00E00000) {
|
2007-10-26 01:14:50 +02:00
|
|
|
return 1;
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
2007-10-26 01:14:50 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static int check_pow_hid0_74xx(CPUPPCState *env)
|
2007-12-10 08:40:16 +01:00
|
|
|
{
|
2019-03-21 12:45:46 +01:00
|
|
|
if (env->spr[SPR_HID0] & 0x00600000) {
|
2007-12-10 08:40:16 +01:00
|
|
|
return 1;
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
2007-12-10 08:40:16 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-19 19:59:05 +02:00
|
|
|
static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
|
|
|
|
{
|
|
|
|
return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/*****************************************************************************/
|
|
|
|
/* PowerPC implementations definitions */
|
2007-03-07 09:32:30 +01:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
#define POWERPC_FAMILY(_name) \
|
|
|
|
static void \
|
|
|
|
glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
|
|
|
|
\
|
|
|
|
static const TypeInfo \
|
|
|
|
glue(glue(ppc_, _name), _cpu_family_type_info) = { \
|
|
|
|
.name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
|
|
|
|
.parent = TYPE_POWERPC_CPU, \
|
|
|
|
.abstract = true, \
|
|
|
|
.class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
|
|
|
|
}; \
|
|
|
|
\
|
|
|
|
static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
|
|
|
|
{ \
|
|
|
|
type_register_static( \
|
|
|
|
&glue(glue(ppc_, _name), _cpu_family_type_info)); \
|
|
|
|
} \
|
|
|
|
\
|
|
|
|
type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
|
|
|
|
\
|
|
|
|
static void glue(glue(ppc_, _name), _cpu_family_class_init)
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_401(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_401_sprs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_4xx_real(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-10-01 03:27:10 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 401";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_401;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_WRTEE | PPC_DCR |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_KEY) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_REAL;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_401x2(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_401x2_sprs(env);
|
|
|
|
register_compress_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Memory management */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_4xx_softmmu(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-10-01 03:27:10 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 401x2";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_401x2;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << 20) |
|
|
|
|
(1ull << MSR_KEY) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_401x3(CPUPPCState *env)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_401_sprs(env);
|
|
|
|
register_401x2_sprs(env);
|
|
|
|
register_compress_sprs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_4xx_softmmu(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-10-01 03:27:10 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 401x3";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_401x3;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << 20) |
|
|
|
|
(1ull << MSR_KEY) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_IOP480(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_401x2_sprs(env);
|
|
|
|
register_compress_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Memory management */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_4xx_softmmu(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-10-01 03:27:10 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(8, 12, 16, 20);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "IOP480";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_IOP480;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << 20) |
|
|
|
|
(1ull << MSR_KEY) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_403(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_403_sprs(env);
|
|
|
|
register_403_real_sprs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_4xx_real(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-10-01 03:27:10 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(8, 12, 16, 20);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 403";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_403;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_PE) |
|
|
|
|
(1ull << MSR_PX) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_REAL;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_403GCX(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_40x_sprs(env);
|
|
|
|
register_401_403_sprs(env);
|
|
|
|
register_403_sprs(env);
|
|
|
|
register_403_real_sprs(env);
|
|
|
|
register_403_mmu_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Bus access control */
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU never does speculative access */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_40x_SGR, "SGR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0xFFFFFFFF);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_40x_DCWR, "DCWR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_4xx_softmmu(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(8, 12, 16, 20);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 403 GCX";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_403GCX;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_4xx_COMMON | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_PE) |
|
|
|
|
(1ull << MSR_PX) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_401;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_405(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_40x_sprs(env);
|
|
|
|
register_405_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Bus access control */
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU never does speculative access */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_40x_SGR, "SGR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0xFFFFFFFF);
|
2012-04-07 09:23:39 +02:00
|
|
|
/* not emulated, as QEMU do not emulate caches */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_40x_DCWR, "DCWR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
init_excp_4xx_softmmu(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(8, 12, 16, 20);
|
|
|
|
SET_WDT_PERIOD(16, 20, 24, 28);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 405";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_405;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_40x;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_405;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_440EP(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_BookE_sprs(env, 0x000000000000FFFFULL);
|
|
|
|
register_440_sprs(env);
|
|
|
|
register_usprgh_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_CCR1, "CCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
init_excp_BookE(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(20, 24, 28, 32);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 440 EP";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_440EP;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_DCR | PPC_WRTEE | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
2017-09-16 16:02:41 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
|
|
|
}
|
|
|
|
|
|
|
|
POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
dc->desc = "PowerPC 460 EX";
|
|
|
|
pcc->init_proc = init_proc_440EP;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_440GP(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_BookE_sprs(env, 0x000000000000FFFFULL);
|
|
|
|
register_440_sprs(env);
|
|
|
|
register_usprgh_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
init_excp_BookE(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* XXX: TODO: allocate internal IRQ controller */
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(20, 24, 28, 32);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 440 GP";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_440GP;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_440x4(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_BookE_sprs(env, 0x000000000000FFFFULL);
|
|
|
|
register_440_sprs(env);
|
|
|
|
register_usprgh_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-11-18 00:02:20 +01:00
|
|
|
#endif
|
|
|
|
init_excp_BookE(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX: TODO: allocate internal IRQ controller */
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(20, 24, 28, 32);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 440x4";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_440x4;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_WRTEE |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_440x5(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_BookE_sprs(env, 0x000000000000FFFFULL);
|
|
|
|
register_440_sprs(env);
|
|
|
|
register_usprgh_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_440_CCR1, "CCR1",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_BookE(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc40x_irq_init(env_archcpu(env));
|
2011-09-13 06:00:32 +02:00
|
|
|
|
|
|
|
SET_FIT_PERIOD(12, 16, 20, 24);
|
|
|
|
SET_WDT_PERIOD(20, 24, 28, 32);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 440x5";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_440x5;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_DCR | PPC_WRTEE | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2014-09-12 21:31:33 +02:00
|
|
|
POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
dc->desc = "PowerPC 440x5 with double precision FPU";
|
|
|
|
pcc->init_proc = init_proc_440x5;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSQRT |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_DCR | PPC_WRTEE | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_MFTB |
|
|
|
|
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
|
|
|
|
PPC_440_SPEC;
|
|
|
|
pcc->insns_flags2 = PPC2_FP_CVT_S64;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_403;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_MPC5xx(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_5xx_8xx_sprs(env);
|
|
|
|
register_5xx_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_MPC5xx(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* XXX: TODO: allocate internal IRQ controller */
|
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "Freescale 5xx cores (aka RCPU)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_MPC5xx;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_MEM_EIEIO | PPC_MEM_SYNC |
|
|
|
|
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_MFTB;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_REAL;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_603;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_505;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_MPC8xx(CPUPPCState *env)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_5xx_8xx_sprs(env);
|
|
|
|
register_8xx_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_MPC8xx(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* XXX: TODO: allocate internal IRQ controller */
|
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_MPC8xx;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
|
|
|
|
PPC_MEM_EIEIO | PPC_MEM_SYNC |
|
|
|
|
PPC_CACHE_ICBI | PPC_MFTB;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_MPC8xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_603;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_860;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Freescale 82xx cores (aka PowerQUICC-II) */
|
2013-02-18 00:16:46 +01:00
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_G2(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_G2_755_sprs(env);
|
|
|
|
register_G2_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* External access control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Hardware implementation register */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_G2(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC G2";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_G2;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_AL) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_G2;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_ec603e;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_G2LE(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_G2_755_sprs(env);
|
|
|
|
register_G2_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* External access control */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Hardware implementation register */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_HID2, "HID2",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2013-04-03 06:03:38 +02:00
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_G2(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC G2LE";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_G2LE;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_AL) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_G2;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_ec603e;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_e200(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2007-09-29 15:06:16 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
|
|
|
register_BookE_sprs(env, 0x000000070000FFFFULL);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
|
2009-03-09 07:27:14 +01:00
|
|
|
&spr_read_spefscr, &spr_write_spefscr,
|
|
|
|
&spr_read_spefscr, &spr_write_spefscr,
|
2007-09-29 15:06:16 +02:00
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_BookE206_sprs(env, 0x0000005D, NULL, 0);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
2007-09-29 15:06:16 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
2007-09-29 15:06:16 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
|
2007-09-29 15:06:16 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-09-29 15:06:16 +02:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
|
2014-01-23 11:43:49 +01:00
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2011-04-30 23:34:58 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000); /* TOFIX */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-09-29 15:06:16 +02:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-09-29 15:06:16 +02:00
|
|
|
env->nb_tlb = 64;
|
|
|
|
env->nb_ways = 1;
|
|
|
|
env->id_tlbs = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_EMB;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2012-06-21 15:17:59 +02:00
|
|
|
init_excp_e200(env, 0xFFFF0000UL);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
2007-09-29 15:06:16 +02:00
|
|
|
/* XXX: TODO: allocate internal IRQ controller */
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e200 core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e200;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* XXX: unimplemented instructions:
|
2013-02-18 00:16:43 +01:00
|
|
|
* dcblc
|
|
|
|
* dcbtlst
|
|
|
|
* dcbtstls
|
|
|
|
* icblc
|
|
|
|
* icbtls
|
|
|
|
* tlbivax
|
|
|
|
* all SPE multiply-accumulate instructions
|
|
|
|
*/
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
|
|
|
|
PPC_SPE | PPC_SPE_SINGLE |
|
|
|
|
PPC_WRTEE | PPC_RFDI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX |
|
|
|
|
PPC_BOOKE;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_SPE) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_860;
|
|
|
|
pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
|
|
|
|
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_e300(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_603_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2009-10-15 19:01:19 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2014-11-06 17:23:50 +01:00
|
|
|
/* Breakpoints */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DABR, "DABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DABR2, "DABR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IABR2, "IABR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_IBCR, "IBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_DBCR, "DBCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-11-18 00:02:20 +01:00
|
|
|
init_excp_603(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e300 core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e300;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_AL) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_603;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_603;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2011-12-22 13:26:17 +01:00
|
|
|
enum fsl_e500_version {
|
|
|
|
fsl_e500v1,
|
|
|
|
fsl_e500v2,
|
|
|
|
fsl_e500mc,
|
2012-06-20 21:55:55 +02:00
|
|
|
fsl_e5500,
|
2017-08-07 17:50:48 +02:00
|
|
|
fsl_e6500,
|
2011-12-22 13:26:17 +01:00
|
|
|
};
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_e500(CPUPPCState *env, int version)
|
2007-11-18 00:02:20 +01:00
|
|
|
{
|
2011-04-30 23:34:58 +02:00
|
|
|
uint32_t tlbncfg[2];
|
2012-06-20 21:55:55 +02:00
|
|
|
uint64_t ivor_mask;
|
2012-06-21 15:17:59 +02:00
|
|
|
uint64_t ivpr_mask = 0xFFFF0000ULL;
|
2012-01-31 03:46:55 +01:00
|
|
|
uint32_t l1cfg0 = 0x3800 /* 8 ways */
|
|
|
|
| 0x0020; /* 32 kb */
|
2014-01-19 17:47:43 +01:00
|
|
|
uint32_t l1cfg1 = 0x3800 /* 8 ways */
|
|
|
|
| 0x0020; /* 32 kb */
|
2017-08-07 17:50:47 +02:00
|
|
|
uint32_t mmucfg = 0;
|
2011-04-30 23:34:58 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
int i;
|
|
|
|
#endif
|
|
|
|
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2011-04-30 23:34:58 +02:00
|
|
|
/*
|
|
|
|
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
|
|
|
|
* complain when accessing them.
|
2021-05-05 17:53:07 +02:00
|
|
|
* register_BookE_sprs(env, 0x0000000F0000FD7FULL);
|
2011-04-30 23:34:58 +02:00
|
|
|
*/
|
2012-06-20 21:55:55 +02:00
|
|
|
switch (version) {
|
2019-03-21 12:45:46 +01:00
|
|
|
case fsl_e500v1:
|
|
|
|
case fsl_e500v2:
|
|
|
|
default:
|
|
|
|
ivor_mask = 0x0000000F0000FFFFULL;
|
|
|
|
break;
|
|
|
|
case fsl_e500mc:
|
|
|
|
case fsl_e5500:
|
|
|
|
ivor_mask = 0x000003FE0000FFFFULL;
|
|
|
|
break;
|
|
|
|
case fsl_e6500:
|
|
|
|
ivor_mask = 0x000003FF0000FFFFULL;
|
|
|
|
break;
|
2012-01-19 18:57:26 +01:00
|
|
|
}
|
2021-05-05 17:53:07 +02:00
|
|
|
register_BookE_sprs(env, ivor_mask);
|
|
|
|
register_usprg3_sprs(env);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Processor identification */
|
|
|
|
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_pir,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
|
2009-03-09 07:27:14 +01:00
|
|
|
&spr_read_spefscr, &spr_write_spefscr,
|
|
|
|
&spr_read_spefscr, &spr_write_spefscr,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
2012-04-19 15:34:06 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Memory management */
|
|
|
|
env->nb_pids = 3;
|
2011-04-30 23:34:58 +02:00
|
|
|
env->nb_ways = 2;
|
|
|
|
env->id_tlbs = 0;
|
|
|
|
switch (version) {
|
2011-12-22 13:26:17 +01:00
|
|
|
case fsl_e500v1:
|
2021-05-05 17:53:07 +02:00
|
|
|
tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
|
|
|
|
tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
|
2011-04-30 23:34:58 +02:00
|
|
|
break;
|
2011-12-22 13:26:17 +01:00
|
|
|
case fsl_e500v2:
|
2021-05-05 17:53:07 +02:00
|
|
|
tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
|
|
|
|
tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
|
2011-12-22 13:26:17 +01:00
|
|
|
break;
|
|
|
|
case fsl_e500mc:
|
2012-06-20 21:55:55 +02:00
|
|
|
case fsl_e5500:
|
2021-05-05 17:53:07 +02:00
|
|
|
tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
|
|
|
|
tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
|
2012-04-19 15:34:06 +02:00
|
|
|
break;
|
2017-08-07 17:50:48 +02:00
|
|
|
case fsl_e6500:
|
|
|
|
mmucfg = 0x6510B45;
|
|
|
|
env->nb_pids = 1;
|
|
|
|
tlbncfg[0] = 0x08052400;
|
|
|
|
tlbncfg[1] = 0x40028040;
|
|
|
|
break;
|
2012-04-19 15:34:06 +02:00
|
|
|
default:
|
2019-03-23 03:07:57 +01:00
|
|
|
cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
|
2019-03-21 12:45:46 +01:00
|
|
|
env->spr[SPR_PVR]);
|
2012-04-19 15:34:06 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Cache sizes */
|
|
|
|
switch (version) {
|
|
|
|
case fsl_e500v1:
|
|
|
|
case fsl_e500v2:
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
break;
|
|
|
|
case fsl_e500mc:
|
2012-06-20 21:55:55 +02:00
|
|
|
case fsl_e5500:
|
2011-12-22 13:26:17 +01:00
|
|
|
env->dcache_line_size = 64;
|
|
|
|
env->icache_line_size = 64;
|
2012-01-31 03:46:55 +01:00
|
|
|
l1cfg0 |= 0x1000000; /* 64 byte cache block size */
|
2014-01-19 17:47:43 +01:00
|
|
|
l1cfg1 |= 0x1000000; /* 64 byte cache block size */
|
2011-04-30 23:34:58 +02:00
|
|
|
break;
|
2017-08-07 17:50:48 +02:00
|
|
|
case fsl_e6500:
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
l1cfg0 |= 0x0F83820;
|
|
|
|
l1cfg1 |= 0x0B83820;
|
|
|
|
break;
|
2011-04-30 23:34:58 +02:00
|
|
|
default:
|
2019-03-23 03:07:57 +01:00
|
|
|
cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
|
2019-03-21 12:45:46 +01:00
|
|
|
env->spr[SPR_PVR]);
|
2011-04-30 23:34:58 +02:00
|
|
|
}
|
2021-05-05 17:53:07 +02:00
|
|
|
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_MCAR, "MCAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
|
2014-01-23 11:43:49 +01:00
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2012-01-31 03:46:55 +01:00
|
|
|
l1cfg0);
|
2014-01-19 17:47:43 +01:00
|
|
|
spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
l1cfg1);
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2011-04-30 23:34:58 +02:00
|
|
|
&spr_read_generic, &spr_write_e500_l1csr0,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2014-01-19 17:49:11 +01:00
|
|
|
&spr_read_generic, &spr_write_e500_l1csr1,
|
2007-11-18 00:02:20 +01:00
|
|
|
0x00000000);
|
2021-02-10 03:45:52 +01:00
|
|
|
if (version != fsl_e500v1 && version != fsl_e500v2) {
|
|
|
|
spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_e500_l2csr0,
|
|
|
|
0x00000000);
|
|
|
|
}
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2011-04-30 23:34:58 +02:00
|
|
|
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_booke206_mmucsr0,
|
|
|
|
0x00000000);
|
2012-06-20 21:55:55 +02:00
|
|
|
spr_register(env, SPR_BOOKE_EPR, "EPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-01-04 11:21:04 +01:00
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2012-06-20 21:55:55 +02:00
|
|
|
0x00000000);
|
|
|
|
/* XXX better abstract into Emb.xxx features */
|
2017-08-07 17:50:48 +02:00
|
|
|
if ((version == fsl_e5500) || (version == fsl_e6500)) {
|
2012-06-20 21:55:55 +02:00
|
|
|
spr_register(env, SPR_BOOKE_EPCR, "EPCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_mas73, &spr_write_mas73,
|
|
|
|
0x00000000);
|
|
|
|
ivpr_mask = (target_ulong)~0xFFFFULL;
|
|
|
|
}
|
2011-04-30 23:34:58 +02:00
|
|
|
|
2017-08-07 17:50:48 +02:00
|
|
|
if (version == fsl_e6500) {
|
|
|
|
/* Thread identification */
|
|
|
|
spr_register(env, SPR_TIR, "TIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000004);
|
|
|
|
spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x7FFFFFFC);
|
|
|
|
}
|
|
|
|
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2011-04-30 23:34:58 +02:00
|
|
|
env->nb_tlb = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_MAS;
|
2011-04-30 23:34:58 +02:00
|
|
|
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
|
|
|
|
env->nb_tlb += booke206_tlb_size(env, i);
|
|
|
|
}
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
2011-04-30 23:34:58 +02:00
|
|
|
|
2012-06-21 15:17:59 +02:00
|
|
|
init_excp_e200(env, ivpr_mask);
|
2009-03-02 17:42:32 +01:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppce500_irq_init(env_archcpu(env));
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2011-04-30 23:34:58 +02:00
|
|
|
static void init_proc_e500v1(CPUPPCState *env)
|
|
|
|
{
|
2011-12-22 13:26:17 +01:00
|
|
|
init_proc_e500(env, fsl_e500v1);
|
2011-04-30 23:34:58 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e500v1 core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e500v1;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
|
|
|
|
PPC_SPE | PPC_SPE_SINGLE |
|
|
|
|
PPC_WRTEE | PPC_RFDI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
|
|
|
|
pcc->insns_flags2 = PPC2_BOOKE206;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_SPE) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_860;
|
|
|
|
pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
|
|
|
|
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2011-04-30 23:34:58 +02:00
|
|
|
static void init_proc_e500v2(CPUPPCState *env)
|
|
|
|
{
|
2011-12-22 13:26:17 +01:00
|
|
|
init_proc_e500(env, fsl_e500v2);
|
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e500v2 core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e500v2;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
|
|
|
|
PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
|
|
|
|
PPC_WRTEE | PPC_RFDI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
|
|
|
|
pcc->insns_flags2 = PPC2_BOOKE206;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_SPE) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DWE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_860;
|
|
|
|
pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
|
|
|
|
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2011-12-22 13:26:17 +01:00
|
|
|
static void init_proc_e500mc(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_proc_e500(env, fsl_e500mc);
|
2011-04-30 23:34:58 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e500mc core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e500mc;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2016-07-22 18:53:51 +02:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
|
|
|
|
PPC_FLOAT_STFIWX | PPC_WAIT |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
|
|
|
|
pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_GS) |
|
|
|
|
(1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PX) |
|
|
|
|
(1ull << MSR_RI);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
/* FIXME: figure out the correct flag for e500mc */
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_e500;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2012-06-20 21:55:55 +02:00
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
static void init_proc_e5500(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_proc_e500(env, fsl_e5500);
|
|
|
|
}
|
2013-02-18 00:16:42 +01:00
|
|
|
|
|
|
|
POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "e5500 core";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_e5500;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2016-07-22 18:53:51 +02:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
|
|
|
|
PPC_FLOAT_STFIWX | PPC_WAIT |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
|
|
|
|
PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
|
2020-04-13 00:35:56 +02:00
|
|
|
pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
|
2014-09-12 21:31:32 +02:00
|
|
|
PPC2_FP_CVT_S64;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_CM) |
|
|
|
|
(1ull << MSR_GS) |
|
|
|
|
(1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PX) |
|
|
|
|
(1ull << MSR_RI);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
/* FIXME: figure out the correct flag for e5500 */
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_e500;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
2017-08-07 17:50:48 +02:00
|
|
|
|
|
|
|
static void init_proc_e6500(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
init_proc_e500(env, fsl_e6500);
|
|
|
|
}
|
|
|
|
|
|
|
|
POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
dc->desc = "e6500 core";
|
|
|
|
pcc->init_proc = init_proc_e6500;
|
|
|
|
pcc->check_pow = check_pow_none;
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
|
|
|
|
PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
|
|
|
|
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
|
|
|
|
PPC_FLOAT_STFIWX | PPC_WAIT |
|
|
|
|
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
|
|
|
|
PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
|
2020-04-13 00:35:56 +02:00
|
|
|
pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
|
2017-08-07 17:50:48 +02:00
|
|
|
PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
|
|
|
|
pcc->msr_mask = (1ull << MSR_CM) |
|
|
|
|
(1ull << MSR_GS) |
|
|
|
|
(1ull << MSR_UCLE) |
|
|
|
|
(1ull << MSR_CE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IS) |
|
|
|
|
(1ull << MSR_DS) |
|
|
|
|
(1ull << MSR_PX) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_VR);
|
|
|
|
pcc->mmu_model = POWERPC_MMU_BOOKE206;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_BOOKE;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_BookE;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_e500;
|
|
|
|
pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
|
|
|
|
}
|
|
|
|
|
2012-06-20 21:55:55 +02:00
|
|
|
#endif
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Non-embedded PowerPC */
|
|
|
|
|
2007-11-19 14:22:47 +01:00
|
|
|
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_601(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_601_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-11-04 03:55:33 +01:00
|
|
|
&spr_read_generic, &spr_write_hid0_601,
|
2007-11-03 14:37:12 +01:00
|
|
|
0x80010080);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_601_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_601_HID5, "HID5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_601(env);
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* XXX: beware that dcache line size is 64
|
2007-11-19 14:22:47 +01:00
|
|
|
* but dcbz uses 32 bytes "sectors"
|
|
|
|
* XXX: this breaks clcs instruction !
|
|
|
|
*/
|
|
|
|
env->dcache_line_size = 32;
|
2007-10-04 02:51:58 +02:00
|
|
|
env->icache_line_size = 64;
|
2007-11-03 14:37:12 +01:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 601";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_601;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
|
|
|
|
PPC_FLOAT |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_601;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_601;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_601;
|
2021-03-15 19:46:00 +01:00
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2007-11-19 14:22:47 +01:00
|
|
|
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_601v(CPUPPCState *env)
|
2007-11-19 14:22:47 +01:00
|
|
|
{
|
|
|
|
init_proc_601(env);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_601_HID15, "HID15",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 601v";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_601v;
|
|
|
|
pcc->check_pow = check_pow_none;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
|
|
|
|
PPC_FLOAT |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_601;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_601;
|
2021-03-15 19:46:00 +01:00
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_602(CPUPPCState *env)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_602_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_602(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
2005-07-02 22:59:34 +02:00
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 602";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_602;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_602_SPEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VSX) |
|
|
|
|
(1ull << MSR_SA) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
/* XXX: 602 MMU is quite specific. Should add a special case */
|
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_602;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_602;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_603(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_603_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_603(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 603";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_603;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_603;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_603;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_603E(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_603_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_603(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 603e";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_603E;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_TGPR) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_603E;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_ec603e;
|
|
|
|
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_604(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_604_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
2007-11-19 14:22:47 +01:00
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-11-19 14:22:47 +01:00
|
|
|
init_excp_604(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-19 14:22:47 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 604";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_604;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_604;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_604;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_604E(CPUPPCState *env)
|
2007-11-19 14:22:47 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_604_sprs(env);
|
2007-11-19 14:22:47 +01:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
|
2007-11-19 14:22:47 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC3, "PMC3",
|
2007-11-19 14:22:47 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC4, "PMC4",
|
2007-11-19 14:22:47 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-19 14:22:47 +01:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_604(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 604E";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_604E;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_604;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_604;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_740(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7x0(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 740";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_740;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_750(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* XXX: high BATs are also present but are known to be bugged on
|
2007-11-21 14:08:23 +01:00
|
|
|
* die version 1.x
|
|
|
|
*/
|
|
|
|
init_excp_7x0(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-21 14:08:23 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 750";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_750;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_750cl(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
|
|
|
/* Those registers are fake on 750CL */
|
|
|
|
spr_register(env, SPR_THRM1, "THRM1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_THRM2, "THRM2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_THRM3, "THRM3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX: not implemented */
|
|
|
|
spr_register(env, SPR_750_TDCL, "TDCL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_750_TDCH, "TDCH",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* DMA */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_WPAR, "WPAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_750_DMAL, "DMAL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_750_DMAU, "DMAU",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750CL_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750CL_HID4, "HID4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Quantization registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR0, "GQR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR1, "GQR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR2, "GQR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR3, "GQR3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR4, "GQR4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR5, "GQR5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR6, "GQR6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_GQR7, "GQR7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* PowerPC 750cl has 8 DBATs and 8 IBATs */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_high_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
init_excp_750cl(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-21 14:08:23 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 750 CL";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_750cl;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* XXX: not implemented:
|
2013-02-18 00:16:43 +01:00
|
|
|
* cache lock instructions:
|
|
|
|
* dcbz_l
|
|
|
|
* floating point paired instructions
|
|
|
|
* psq_lux
|
|
|
|
* psq_lx
|
|
|
|
* psq_stux
|
|
|
|
* psq_stx
|
|
|
|
* ps_abs
|
|
|
|
* ps_add
|
|
|
|
* ps_cmpo0
|
|
|
|
* ps_cmpo1
|
|
|
|
* ps_cmpu0
|
|
|
|
* ps_cmpu1
|
|
|
|
* ps_div
|
|
|
|
* ps_madd
|
|
|
|
* ps_madds0
|
|
|
|
* ps_madds1
|
|
|
|
* ps_merge00
|
|
|
|
* ps_merge01
|
|
|
|
* ps_merge10
|
|
|
|
* ps_merge11
|
|
|
|
* ps_mr
|
|
|
|
* ps_msub
|
|
|
|
* ps_mul
|
|
|
|
* ps_muls0
|
|
|
|
* ps_muls1
|
|
|
|
* ps_nabs
|
|
|
|
* ps_neg
|
|
|
|
* ps_nmadd
|
|
|
|
* ps_nmsub
|
|
|
|
* ps_res
|
|
|
|
* ps_rsqrte
|
|
|
|
* ps_sel
|
|
|
|
* ps_sub
|
|
|
|
* ps_sum0
|
|
|
|
* ps_sum1
|
|
|
|
*/
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_750cx(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* This register is not implemented but is present for compatibility */
|
|
|
|
spr_register(env, SPR_SDA, "SDA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_high_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
init_excp_750cx(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-21 14:08:23 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 750CX";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_750cx;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_750fx(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_THRM4, "THRM4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2007-11-21 14:08:23 +01:00
|
|
|
spr_register(env, SPR_750FX_HID2, "HID2",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_high_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
init_excp_7x0(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 750FX";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_750fx;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_750gx(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented (XXX: different from 750fx) */
|
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
2007-11-21 14:08:23 +01:00
|
|
|
0x00000000);
|
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_750_THRM4, "THRM4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented (XXX: different from 750fx) */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented (XXX: different from 750fx) */
|
|
|
|
spr_register(env, SPR_750FX_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_high_BATs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
init_excp_7x0(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-21 14:08:23 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 750GX";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_750gx;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_7x0;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_745(CPUPPCState *env)
|
2007-11-21 14:08:23 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
|
|
|
register_G2_755_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-11-21 14:08:23 +01:00
|
|
|
init_excp_7x5(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-11-21 14:08:23 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 745";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_745;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_7x5;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_755(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
|
|
|
register_G2_755_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* L2 cache control */
|
|
|
|
/* XXX : not implemented */
|
2007-11-21 14:08:23 +01:00
|
|
|
spr_register(env, SPR_L2CR, "L2CR",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-09-25 15:41:12 +02:00
|
|
|
&spr_read_generic, spr_access_nop,
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2PMCR, "L2PMCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-11-21 14:08:23 +01:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID2, "HID2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_6xx_7xx_soft_tlb(env, 64, 2);
|
2007-10-08 04:23:00 +02:00
|
|
|
init_excp_7x5(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 755";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_755;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_7x5;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_750;
|
|
|
|
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
|
|
|
|
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7400(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_UBAMR, "UBAMR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX: this seems not implemented on all revisions. */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MSSCR1, "MSSCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7400(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7400 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7400;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7410(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_UBAMR, "UBAMR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Thermal management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_thrm_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* L2PMCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L2PMCR, "L2PMCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* LDSTDB */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTDB, "LDSTDB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7400(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7410 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7410;
|
|
|
|
pcc->check_pow = check_pow_hid0;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7440(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_UBAMR, "UBAMR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* LDSTCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* ICTRL */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* MSSSR0 */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* PMC */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2007-10-05 15:09:54 +02:00
|
|
|
init_excp_7450(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7440 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7440;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7450(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Level 3 cache control */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_l3_ctrl(env);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* L3ITCR1 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3ITCR2 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3ITCR3 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3OHCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3OHCR, "L3OHCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_UBAMR, "UBAMR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* LDSTCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* ICTRL */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* MSSSR0 */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* PMC */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7450(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7450 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7450;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7445(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* LDSTCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* ICTRL */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* MSSSR0 */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* PMC */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRGs */
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7450(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7445 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7445;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7455(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Level 3 cache control */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_l3_ctrl(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* LDSTCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* ICTRL */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* MSSSR0 */
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* PMC */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-01 06:48:45 +02:00
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRGs */
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2007-09-29 15:06:16 +02:00
|
|
|
init_excp_7450(env);
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7455 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7455;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_7457(CPUPPCState *env)
|
2007-12-10 08:40:16 +01:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* Level 3 cache control */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_l3_ctrl(env);
|
2007-12-10 08:40:16 +01:00
|
|
|
/* L3ITCR1 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3ITCR2 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3ITCR3 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* L3OHCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_L3OHCR, "L3OHCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* LDSTCR */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* ICTRL */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* MSSSR0 */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* PMC */
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
2007-12-10 08:40:16 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
2007-12-10 08:40:16 +01:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
2007-12-10 08:40:16 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
2007-12-10 08:40:16 +01:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRGs */
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2007-12-10 08:40:16 +01:00
|
|
|
init_excp_7450(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2007-12-10 08:40:16 +01:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "PowerPC 7457 (aka G4)";
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_7457;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_e600(CPUPPCState *env)
|
2013-06-24 23:15:54 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_7xx_sprs(env);
|
2013-06-24 23:15:54 +02:00
|
|
|
/* Time base */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_tbl(env);
|
2013-06-24 23:15:54 +02:00
|
|
|
/* 74xx specific SPR */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_74xx_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
vscr_init(env, 0x00010000);
|
2013-06-24 23:15:54 +02:00
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_UBAMR, "UBAMR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_ICTRL, "ICTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC5, "PMC5",
|
2013-06-24 23:15:54 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
|
2013-06-24 23:15:54 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_PMC6, "PMC6",
|
2013-06-24 23:15:54 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* XXX : not implemented */
|
2014-06-04 14:50:36 +02:00
|
|
|
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
|
2013-06-24 23:15:54 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* SPRGs */
|
|
|
|
spr_register(env, SPR_SPRG4, "SPRG4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG5, "SPRG5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG6, "SPRG6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG7, "SPRG7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
/* Memory management */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_low_BATs(env);
|
|
|
|
register_high_BATs(env);
|
|
|
|
register_74xx_soft_tlb(env, 128, 2);
|
2013-06-24 23:15:54 +02:00
|
|
|
init_excp_7450(env);
|
|
|
|
env->dcache_line_size = 32;
|
|
|
|
env->icache_line_size = 32;
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc6xx_irq_init(env_archcpu(env));
|
2013-06-24 23:15:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
dc->desc = "PowerPC e600";
|
|
|
|
pcc->init_proc = init_proc_e600;
|
|
|
|
pcc->check_pow = check_pow_hid0_74xx;
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI |
|
|
|
|
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_MEM_TLBIA | PPC_74xx_TLB |
|
|
|
|
PPC_SEGMENT | PPC_EXTERN |
|
|
|
|
PPC_ALTIVEC;
|
|
|
|
pcc->insns_flags2 = PPC_NONE;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_ILE) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_EP) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2013-06-24 23:15:54 +02:00
|
|
|
pcc->mmu_model = POWERPC_MMU_32B;
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
|
|
|
|
#endif
|
|
|
|
pcc->excp_model = POWERPC_EXCP_74xx;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc_7400;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-10-08 01:10:08 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
#define POWERPC970_HID5_INIT 0x00000080
|
|
|
|
#else
|
|
|
|
#define POWERPC970_HID5_INIT 0x00000000
|
|
|
|
#endif
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static int check_pow_970(CPUPPCState *env)
|
2007-10-26 01:14:50 +02:00
|
|
|
{
|
2014-06-04 14:50:37 +02:00
|
|
|
if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
|
2007-10-26 01:14:50 +02:00
|
|
|
return 1;
|
2014-06-04 14:50:37 +02:00
|
|
|
}
|
2007-10-26 01:14:50 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_hid_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
/* Hardware implementation registers */
|
|
|
|
/* XXX : not implemented */
|
|
|
|
spr_register(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2007-10-03 22:27:44 +02:00
|
|
|
&spr_read_generic, &spr_write_clear,
|
2007-10-04 02:51:58 +02:00
|
|
|
0x60000000);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_HID1, "HID1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2007-10-04 03:50:03 +02:00
|
|
|
spr_register(env, SPR_970_HID5, "HID5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2007-10-08 01:10:08 +02:00
|
|
|
POWERPC970_HID5_INIT);
|
2014-06-04 14:50:38 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_hior_sprs(CPUPPCState *env)
|
2014-06-04 14:50:38 +02:00
|
|
|
{
|
2007-10-06 00:06:02 +02:00
|
|
|
spr_register(env, SPR_HIOR, "SPR_HIOR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2009-02-28 19:39:42 +01:00
|
|
|
&spr_read_hior, &spr_write_hior,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:38 +02:00
|
|
|
}
|
2013-02-18 00:16:42 +01:00
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_ctrl_sprs(CPUPPCState *env)
|
2014-06-04 14:50:38 +02:00
|
|
|
{
|
2009-03-07 21:54:03 +01:00
|
|
|
spr_register(env, SPR_CTRL, "SPR_CTRL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2013-12-23 03:42:22 +01:00
|
|
|
SPR_NOACCESS, &spr_write_generic,
|
2009-03-07 21:54:03 +01:00
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
|
2014-06-04 14:50:39 +02:00
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
2009-03-07 21:54:03 +01:00
|
|
|
0x00000000);
|
2014-06-04 14:50:38 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_altivec_sprs(CPUPPCState *env)
|
2014-06-04 14:50:38 +02:00
|
|
|
{
|
|
|
|
if (!(env->insns_flags & PPC_ALTIVEC)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-06-04 14:51:02 +02:00
|
|
|
spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_VRSAVE, 0x00000000);
|
2014-06-04 14:50:38 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_dbg_sprs(CPUPPCState *env)
|
2014-06-04 14:50:40 +02:00
|
|
|
{
|
2014-06-04 14:51:03 +02:00
|
|
|
/*
|
|
|
|
* TODO: different specs define different scopes for these,
|
|
|
|
* will have to address this:
|
|
|
|
* 970: super/write and super/read
|
|
|
|
* powerisa 2.03..2.04: hypv/write and super/read.
|
|
|
|
* powerisa 2.05 and newer: hypv/write and hypv/read.
|
|
|
|
*/
|
2014-06-04 14:50:40 +02:00
|
|
|
spr_register_kvm(env, SPR_DABR, "DABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DABR, 0x00000000);
|
2014-06-04 14:51:03 +02:00
|
|
|
spr_register_kvm(env, SPR_DABRX, "DABRX",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DABRX, 0x00000000);
|
2014-06-04 14:50:40 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_207_dbg_sprs(CPUPPCState *env)
|
2016-03-21 13:52:33 +01:00
|
|
|
{
|
2021-04-12 13:44:32 +02:00
|
|
|
spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
|
2016-03-21 13:52:33 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DAWR, 0x00000000);
|
2021-04-12 13:44:32 +02:00
|
|
|
spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
|
2016-03-21 13:52:33 +01:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DAWRX, 0x00000000);
|
2016-03-21 13:52:39 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_CIABR, 0x00000000);
|
2016-03-21 13:52:33 +01:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_dbg_sprs(CPUPPCState *env)
|
2014-06-04 14:50:40 +02:00
|
|
|
{
|
|
|
|
/* Breakpoints */
|
|
|
|
spr_register(env, SPR_IABR, "IABR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
|
2014-06-04 14:50:40 +02:00
|
|
|
{
|
2014-06-04 14:50:47 +02:00
|
|
|
spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_MMCR0, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_MMCR1, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_MMCRA, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC1, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC2, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC3, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC4, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC5, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC6, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_SIAR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_SDAR, 0x00000000);
|
2014-06-04 14:50:40 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_pmu_user_sprs(CPUPPCState *env)
|
2014-06-04 14:50:40 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:42 +02:00
|
|
|
spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:40 +02:00
|
|
|
spr_register(env, SPR_POWER_UPMC1, "UPMC1",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_POWER_UPMC2, "UPMC2",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_POWER_UPMC3, "UPMC3",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_POWER_UPMC4, "UPMC4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:42 +02:00
|
|
|
spr_register(env, SPR_POWER_UPMC5, "UPMC5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_POWER_UPMC6, "UPMC6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:40 +02:00
|
|
|
spr_register(env, SPR_POWER_USIAR, "USIAR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:42 +02:00
|
|
|
spr_register(env, SPR_POWER_USDAR, "USDAR",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:40 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_pmu_sup_sprs(CPUPPCState *env)
|
2014-06-04 14:50:43 +02:00
|
|
|
{
|
2014-06-04 14:50:47 +02:00
|
|
|
spr_register_kvm(env, SPR_970_PMC7, "PMC7",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC7, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_970_PMC8, "PMC8",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PMC8, 0x00000000);
|
2014-06-04 14:50:43 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_pmu_user_sprs(CPUPPCState *env)
|
2014-06-04 14:50:43 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_970_UPMC7, "UPMC7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_970_UPMC8, "UPMC8",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_pmu_sup_sprs(CPUPPCState *env)
|
2014-06-04 14:50:58 +02:00
|
|
|
{
|
|
|
|
spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_MMCR2, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_MMCRS, 0x00000000);
|
2016-03-02 21:19:22 +01:00
|
|
|
spr_register_kvm(env, SPR_POWER_SIER, "SIER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_SIER, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_SPMC1, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_SPMC2, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_TACR, "TACR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_TACR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_TCSCR, "TCSCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_TCSCR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_CSIGR, "CSIGR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_CSIGR, 0x00000000);
|
2014-06-04 14:50:58 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_pmu_user_sprs(CPUPPCState *env)
|
2014-06-04 14:50:58 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, &spr_write_ureg,
|
|
|
|
0x00000000);
|
2016-03-02 21:19:22 +01:00
|
|
|
spr_register(env, SPR_POWER_USIER, "USIER",
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2014-06-04 14:50:58 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power5p_ear_sprs(CPUPPCState *env)
|
2014-06-04 14:50:40 +02:00
|
|
|
{
|
|
|
|
/* External access control */
|
|
|
|
spr_register(env, SPR_EAR, "EAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power5p_tb_sprs(CPUPPCState *env)
|
2019-11-28 14:46:57 +01:00
|
|
|
{
|
|
|
|
/* TBU40 (High 40 bits of the Timebase register */
|
|
|
|
spr_register_hv(env, SPR_TBU40, "TBU40",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbu40,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_970_lpar_sprs(CPUPPCState *env)
|
2016-06-27 08:55:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2019-12-11 11:55:05 +01:00
|
|
|
/*
|
|
|
|
* PPC970: HID4 covers things later controlled by the LPCR and
|
|
|
|
* RMOR in later CPUs, but with a different encoding. We only
|
|
|
|
* support the 970 in "Apple mode" which has all hypervisor
|
|
|
|
* facilities disabled by strapping, so we can basically just
|
|
|
|
* ignore it
|
|
|
|
*/
|
2016-06-27 08:55:16 +02:00
|
|
|
spr_register(env, SPR_970_HID4, "HID4",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2019-12-11 11:55:05 +01:00
|
|
|
&spr_read_generic, &spr_write_generic,
|
2016-06-27 08:55:16 +02:00
|
|
|
0x00000000);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power5p_lpar_sprs(CPUPPCState *env)
|
2016-06-27 08:55:16 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* Logical partitionning */
|
2016-06-27 08:55:20 +02:00
|
|
|
spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_lpcr,
|
|
|
|
KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
|
2016-06-27 08:55:19 +02:00
|
|
|
spr_register_hv(env, SPR_HDEC, "HDEC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_hdecr, &spr_write_hdecr, 0);
|
2016-06-27 08:55:14 +02:00
|
|
|
#endif
|
2016-06-27 08:55:16 +02:00
|
|
|
}
|
2016-06-27 08:55:14 +02:00
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_ids_sprs(CPUPPCState *env)
|
2014-06-04 14:50:48 +02:00
|
|
|
{
|
2016-06-27 08:55:14 +02:00
|
|
|
/* FIXME: Will need to deal with thread vs core only SPRs */
|
|
|
|
|
2014-06-04 14:50:48 +02:00
|
|
|
/* Processor identification */
|
2016-06-27 08:55:14 +02:00
|
|
|
spr_register_hv(env, SPR_PIR, "PIR",
|
2014-06-04 14:50:48 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2018-06-08 11:46:55 +02:00
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2016-06-27 08:55:14 +02:00
|
|
|
&spr_read_generic, NULL,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HID0, "HID0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_TSCR, "TSCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HMER, "HMER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_hmer,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HMEER, "HMEER",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_TFMR, "TFMR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_LPIDR, "LPIDR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2019-02-15 18:00:26 +01:00
|
|
|
&spr_read_generic, &spr_write_lpidr,
|
2016-06-27 08:55:14 +02:00
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HFSCR, "HFSCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_MMCRC, "MMCRC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_MMCRH, "MMCRH",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HSRR0, "HSRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HSRR1, "HSRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HDAR, "HDAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_HDSISR, "HDSISR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2020-01-06 03:14:16 +01:00
|
|
|
spr_register_hv(env, SPR_HRMOR, "HRMOR",
|
2016-06-27 08:55:14 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
2020-01-06 03:14:16 +01:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_rmor_sprs(CPUPPCState *env)
|
2020-01-06 03:14:16 +01:00
|
|
|
{
|
|
|
|
spr_register_hv(env, SPR_RMOR, "RMOR",
|
2016-06-27 08:55:14 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2014-06-04 14:50:48 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_ids_sprs(CPUPPCState *env)
|
2014-06-04 14:50:55 +02:00
|
|
|
{
|
|
|
|
/* Thread identification */
|
|
|
|
spr_register(env, SPR_TIR, "TIR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_book3s_purr_sprs(CPUPPCState *env)
|
2014-06-04 14:50:48 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
|
2019-11-28 14:46:55 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_PURR, "PURR",
|
|
|
|
&spr_read_purr, SPR_NOACCESS,
|
|
|
|
&spr_read_purr, SPR_NOACCESS,
|
|
|
|
&spr_read_purr, &spr_write_purr,
|
|
|
|
KVM_REG_PPC_PURR, 0x00000000);
|
|
|
|
spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
|
|
|
|
&spr_read_purr, SPR_NOACCESS,
|
|
|
|
&spr_read_purr, SPR_NOACCESS,
|
|
|
|
&spr_read_purr, &spr_write_purr,
|
|
|
|
KVM_REG_PPC_SPURR, 0x00000000);
|
2014-06-04 14:50:48 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power6_dbg_sprs(CPUPPCState *env)
|
2014-06-04 14:50:50 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register(env, SPR_CFAR, "SPR_CFAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_cfar, &spr_write_cfar,
|
|
|
|
0x00000000);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power5p_common_sprs(CPUPPCState *env)
|
2014-06-04 14:50:50 +02:00
|
|
|
{
|
2014-06-04 14:51:02 +02:00
|
|
|
spr_register_kvm(env, SPR_PPR, "PPR",
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PPR, 0x00000000);
|
2014-06-04 14:50:50 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power6_common_sprs(CPUPPCState *env)
|
2014-06-04 14:50:50 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DSCR, 0x00000000);
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* Register PCR to report POWERPC_EXCP_PRIV_REG instead of
|
2018-06-04 10:45:13 +02:00
|
|
|
* POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
|
2014-06-04 14:50:50 +02:00
|
|
|
*/
|
2018-06-04 10:45:13 +02:00
|
|
|
spr_register_hv(env, SPR_PCR, "PCR",
|
2014-06-04 14:50:50 +02:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2018-06-04 10:45:13 +02:00
|
|
|
&spr_read_generic, &spr_write_pcr,
|
2014-06-04 14:50:50 +02:00
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_tce_address_control_sprs(CPUPPCState *env)
|
2014-06-04 14:50:49 +02:00
|
|
|
{
|
2016-03-02 21:19:21 +01:00
|
|
|
spr_register_kvm(env, SPR_TAR, "TAR",
|
|
|
|
&spr_read_tar, &spr_write_tar,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_TAR, 0x00000000);
|
2014-06-04 14:50:49 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_tm_sprs(CPUPPCState *env)
|
2014-06-04 14:50:59 +02:00
|
|
|
{
|
|
|
|
spr_register_kvm(env, SPR_TFHAR, "TFHAR",
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
KVM_REG_PPC_TFHAR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_TFIAR, "TFIAR",
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
KVM_REG_PPC_TFIAR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_TEXASR, "TEXASR",
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
&spr_read_tm, &spr_write_tm,
|
|
|
|
KVM_REG_PPC_TEXASR, 0x00000000);
|
|
|
|
spr_register(env, SPR_TEXASRU, "TEXASRU",
|
|
|
|
&spr_read_tm_upper32, &spr_write_tm_upper32,
|
|
|
|
&spr_read_tm_upper32, &spr_write_tm_upper32,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_ebb_sprs(CPUPPCState *env)
|
2014-06-04 14:51:01 +02:00
|
|
|
{
|
|
|
|
spr_register(env, SPR_BESCRS, "BESCRS",
|
|
|
|
&spr_read_ebb, &spr_write_ebb,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BESCRSU, "BESCRSU",
|
|
|
|
&spr_read_ebb_upper32, &spr_write_ebb_upper32,
|
|
|
|
&spr_read_prev_upper32, &spr_write_prev_upper32,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BESCRR, "BESCRR",
|
|
|
|
&spr_read_ebb, &spr_write_ebb,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_BESCRRU, "BESCRRU",
|
|
|
|
&spr_read_ebb_upper32, &spr_write_ebb_upper32,
|
|
|
|
&spr_read_prev_upper32, &spr_write_prev_upper32,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_EBBHR, "EBBHR",
|
|
|
|
&spr_read_ebb, &spr_write_ebb,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_EBBHR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_EBBRR, "EBBRR",
|
|
|
|
&spr_read_ebb, &spr_write_ebb,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_EBBRR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_BESCR, "BESCR",
|
|
|
|
&spr_read_ebb, &spr_write_ebb,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_BESCR, 0x00000000);
|
|
|
|
}
|
|
|
|
|
2015-03-02 07:55:38 +01:00
|
|
|
/* Virtual Time Base */
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_vtb_sprs(CPUPPCState *env)
|
2015-03-02 07:55:38 +01:00
|
|
|
{
|
2019-11-28 14:46:54 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_VTB, "VTB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_vtb, SPR_NOACCESS,
|
|
|
|
&spr_read_vtb, &spr_write_vtb,
|
|
|
|
KVM_REG_PPC_VTB, 0x00000000);
|
2015-03-02 07:55:38 +01:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_fscr_sprs(CPUPPCState *env)
|
2014-06-04 14:50:56 +02:00
|
|
|
{
|
2014-06-04 14:50:57 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
target_ulong initval = 1ULL << FSCR_TAR;
|
|
|
|
#else
|
|
|
|
target_ulong initval = 0;
|
|
|
|
#endif
|
2014-06-04 14:50:56 +02:00
|
|
|
spr_register_kvm(env, SPR_FSCR, "FSCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
2014-06-04 14:50:57 +02:00
|
|
|
KVM_REG_PPC_FSCR, initval);
|
2014-06-04 14:50:56 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_pspb_sprs(CPUPPCState *env)
|
2016-03-02 21:19:20 +01:00
|
|
|
{
|
|
|
|
spr_register_kvm(env, SPR_PSPB, "PSPB",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic32,
|
|
|
|
KVM_REG_PPC_PSPB, 0);
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_dpdes_sprs(CPUPPCState *env)
|
2019-08-16 08:17:33 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* Directed Privileged Door-bell Exception State, used for IPI */
|
2020-01-20 11:49:34 +01:00
|
|
|
spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dpdes, SPR_NOACCESS,
|
|
|
|
&spr_read_dpdes, &spr_write_dpdes,
|
|
|
|
KVM_REG_PPC_DPDES, 0x00000000);
|
2019-08-16 08:17:33 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_ic_sprs(CPUPPCState *env)
|
2016-03-21 13:52:35 +01:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register_hv(env, SPR_IC, "IC",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0);
|
2016-03-22 15:23:13 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_book4_sprs(CPUPPCState *env)
|
2016-03-22 15:23:13 +01:00
|
|
|
{
|
|
|
|
/* Add a number of P8 book4 registers */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2016-03-21 13:52:40 +01:00
|
|
|
spr_register_kvm(env, SPR_ACOP, "ACOP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_ACOP, 0);
|
|
|
|
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
2017-04-13 08:02:36 +02:00
|
|
|
&spr_read_generic, &spr_write_pidr,
|
2016-03-21 13:52:40 +01:00
|
|
|
KVM_REG_PPC_PID, 0);
|
|
|
|
spr_register_kvm(env, SPR_WORT, "WORT",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_WORT, 0);
|
2016-03-21 13:52:35 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power7_book4_sprs(CPUPPCState *env)
|
2016-06-07 04:50:23 +02:00
|
|
|
{
|
|
|
|
/* Add a number of P7 book4 registers */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register_kvm(env, SPR_ACOP, "ACOP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_ACOP, 0);
|
|
|
|
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_PID, 0);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power8_rpr_sprs(CPUPPCState *env)
|
2016-06-27 08:55:14 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register_hv(env, SPR_RPR, "RPR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000103070F1F3F);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-05-05 17:53:07 +02:00
|
|
|
static void register_power9_mmu_sprs(CPUPPCState *env)
|
2018-04-24 13:30:42 +02:00
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* Partition Table Control */
|
2018-10-08 05:25:38 +02:00
|
|
|
spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_ptcr,
|
|
|
|
KVM_REG_PPC_PTCR, 0x00000000);
|
2019-11-28 14:46:56 +01:00
|
|
|
/* Address Segment Descriptor Register */
|
|
|
|
spr_register_hv(env, SPR_ASDR, "ASDR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x0000000000000000);
|
2018-04-24 13:30:42 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-03-01 07:54:37 +01:00
|
|
|
static void init_proc_book3s_common(CPUPPCState *env)
|
2014-06-04 14:50:38 +02:00
|
|
|
{
|
2021-05-05 17:53:07 +02:00
|
|
|
register_ne_601_sprs(env);
|
|
|
|
register_tbl(env);
|
|
|
|
register_usprg3_sprs(env);
|
|
|
|
register_book3s_altivec_sprs(env);
|
|
|
|
register_book3s_pmu_sup_sprs(env);
|
|
|
|
register_book3s_pmu_user_sprs(env);
|
|
|
|
register_book3s_ctrl_sprs(env);
|
2021-04-30 21:35:31 +02:00
|
|
|
/*
|
|
|
|
* Can't find information on what this should be on reset. This
|
|
|
|
* value is the one used by 74xx processors.
|
|
|
|
*/
|
|
|
|
vscr_init(env, 0x00010000);
|
2017-03-01 07:54:37 +01:00
|
|
|
}
|
2014-06-04 14:50:40 +02:00
|
|
|
|
2017-03-01 07:54:37 +01:00
|
|
|
static void init_proc_970(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_book3s_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* 970 Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_970_hid_sprs(env);
|
|
|
|
register_970_hior_sprs(env);
|
|
|
|
register_low_BATs(env);
|
|
|
|
register_970_pmu_sup_sprs(env);
|
|
|
|
register_970_pmu_user_sprs(env);
|
|
|
|
register_970_lpar_sprs(env);
|
|
|
|
register_970_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* env variables */
|
2007-10-04 02:51:58 +02:00
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2017-03-01 07:54:37 +01:00
|
|
|
/* Allocate hardware IRQ controller */
|
|
|
|
init_excp_970(env);
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc970_irq_init(env_archcpu(env));
|
2014-06-04 14:50:45 +02:00
|
|
|
}
|
|
|
|
|
2014-06-04 14:50:37 +02:00
|
|
|
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
|
2013-02-18 00:16:42 +01:00
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2014-06-04 14:50:37 +02:00
|
|
|
dc->desc = "PowerPC 970";
|
|
|
|
pcc->init_proc = init_proc_970;
|
|
|
|
pcc->check_pow = check_pow_970;
|
2013-02-18 00:16:43 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_64B | PPC_ALTIVEC |
|
|
|
|
PPC_SEGMENT_64B | PPC_SLBI;
|
2014-09-12 21:31:32 +02:00
|
|
|
pcc->insns_flags2 = PPC2_FP_CVT_S64;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI);
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_64B;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
|
2018-03-23 03:59:20 +01:00
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_basic;
|
2013-03-13 01:40:33 +01:00
|
|
|
#endif
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_970;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_970;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2014-04-08 01:42:53 +02:00
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x10000;
|
2013-02-18 00:16:42 +01:00
|
|
|
}
|
|
|
|
|
2013-08-01 03:42:02 +02:00
|
|
|
static void init_proc_power5plus(CPUPPCState *env)
|
|
|
|
{
|
2017-03-01 07:54:37 +01:00
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_book3s_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* POWER5+ Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_970_hid_sprs(env);
|
|
|
|
register_970_hior_sprs(env);
|
|
|
|
register_low_BATs(env);
|
|
|
|
register_970_pmu_sup_sprs(env);
|
|
|
|
register_970_pmu_user_sprs(env);
|
|
|
|
register_power5p_common_sprs(env);
|
|
|
|
register_power5p_lpar_sprs(env);
|
|
|
|
register_power5p_ear_sprs(env);
|
|
|
|
register_power5p_tb_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* env variables */
|
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
|
|
|
|
|
|
|
/* Allocate hardware IRQ controller */
|
|
|
|
init_excp_970(env);
|
2019-03-23 03:07:57 +01:00
|
|
|
ppc970_irq_init(env_archcpu(env));
|
2013-08-01 03:42:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
|
2013-10-15 18:33:36 +02:00
|
|
|
dc->fw_name = "PowerPC,POWER5";
|
2013-08-01 03:42:02 +02:00
|
|
|
dc->desc = "POWER5+";
|
|
|
|
pcc->init_proc = init_proc_power5plus;
|
2014-06-04 14:50:46 +02:00
|
|
|
pcc->check_pow = check_pow_970;
|
2013-08-01 03:42:02 +02:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
|
|
|
PPC_64B |
|
|
|
|
PPC_SEGMENT_64B | PPC_SLBI;
|
2014-09-12 21:31:32 +02:00
|
|
|
pcc->insns_flags2 = PPC2_FP_CVT_S64;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_POW) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI);
|
2020-01-06 06:35:10 +01:00
|
|
|
pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
|
|
|
|
LPCR_RMI | LPCR_HDICE;
|
2015-10-22 09:30:58 +02:00
|
|
|
pcc->mmu_model = POWERPC_MMU_2_03;
|
2013-08-01 03:42:02 +02:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
|
2018-03-23 03:59:20 +01:00
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_basic;
|
2019-03-01 03:43:15 +01:00
|
|
|
pcc->lrg_decr_bits = 32;
|
2013-08-01 03:42:02 +02:00
|
|
|
#endif
|
|
|
|
pcc->excp_model = POWERPC_EXCP_970;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_970;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK;
|
2014-04-08 01:42:53 +02:00
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x10000;
|
2013-08-01 03:42:02 +02:00
|
|
|
}
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
static void init_proc_POWER7(CPUPPCState *env)
|
2011-04-01 06:15:19 +02:00
|
|
|
{
|
2017-03-01 07:54:37 +01:00
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_book3s_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* POWER7 Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_ids_sprs(env);
|
|
|
|
register_rmor_sprs(env);
|
|
|
|
register_amr_sprs(env);
|
|
|
|
register_book3s_purr_sprs(env);
|
|
|
|
register_power5p_common_sprs(env);
|
|
|
|
register_power5p_lpar_sprs(env);
|
|
|
|
register_power5p_ear_sprs(env);
|
|
|
|
register_power5p_tb_sprs(env);
|
|
|
|
register_power6_common_sprs(env);
|
|
|
|
register_power6_dbg_sprs(env);
|
|
|
|
register_power7_book4_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* env variables */
|
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
|
|
|
|
|
|
|
/* Allocate hardware IRQ controller */
|
|
|
|
init_excp_POWER7(env);
|
2019-03-23 03:07:57 +01:00
|
|
|
ppcPOWER7_irq_init(env_archcpu(env));
|
2011-04-01 06:15:19 +02:00
|
|
|
}
|
|
|
|
|
2014-07-03 16:48:55 +02:00
|
|
|
static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
|
|
|
|
{
|
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-21 23:48:55 +02:00
|
|
|
static bool cpu_has_work_POWER7(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (cs->halted) {
|
|
|
|
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:42 +01:00
|
|
|
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-02-18 00:16:46 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
2016-06-21 23:48:55 +02:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-02-18 00:16:42 +01:00
|
|
|
|
2013-10-15 18:33:36 +02:00
|
|
|
dc->fw_name = "PowerPC,POWER7";
|
2013-02-18 00:16:46 +01:00
|
|
|
dc->desc = "POWER7";
|
2014-07-03 16:48:55 +02:00
|
|
|
pcc->pvr_match = ppc_pvr_match_power7;
|
2016-06-07 17:39:37 +02:00
|
|
|
pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
|
|
|
|
pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
|
2013-02-18 00:16:42 +01:00
|
|
|
pcc->init_proc = init_proc_POWER7;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2016-06-21 23:48:55 +02:00
|
|
|
cc->has_work = cpu_has_work_POWER7;
|
2013-04-01 07:06:23 +02:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
2014-01-07 17:06:09 +01:00
|
|
|
PPC_FLOAT_FRSQRTES |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_FLOAT_STFIWX |
|
2014-01-07 17:06:05 +01:00
|
|
|
PPC_FLOAT_EXT |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
2016-06-07 04:50:24 +02:00
|
|
|
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
|
2013-02-18 00:16:43 +01:00
|
|
|
PPC_SEGMENT_64B | PPC_SLBI |
|
2016-06-21 23:48:52 +02:00
|
|
|
PPC_POPCNTB | PPC_POPCNTWD |
|
|
|
|
PPC_CILDST;
|
2014-01-07 17:05:49 +01:00
|
|
|
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
|
2014-01-07 17:05:55 +01:00
|
|
|
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
|
2014-01-07 17:06:06 +01:00
|
|
|
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
|
2016-06-21 23:48:55 +02:00
|
|
|
PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
|
|
|
|
PPC2_PM_ISA206;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_VSX) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2020-01-06 06:35:10 +01:00
|
|
|
pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
|
|
|
|
LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
|
|
|
|
LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
|
|
|
|
LPCR_MER | LPCR_TC |
|
|
|
|
LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
|
|
|
|
pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
|
2013-02-18 00:16:45 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_2_06;
|
2013-03-13 01:40:33 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
|
2018-03-23 03:31:52 +01:00
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
|
2019-03-01 03:43:15 +01:00
|
|
|
pcc->lrg_decr_bits = 32;
|
2013-11-19 02:39:15 +01:00
|
|
|
#endif
|
|
|
|
pcc->excp_model = POWERPC_EXCP_POWER7;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
|
|
|
|
POWERPC_FLAG_VSX;
|
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x8000;
|
2014-05-19 19:59:05 +02:00
|
|
|
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
|
2013-11-19 02:39:15 +01:00
|
|
|
}
|
|
|
|
|
2014-02-10 18:26:54 +01:00
|
|
|
static void init_proc_POWER8(CPUPPCState *env)
|
|
|
|
{
|
2017-03-01 07:54:37 +01:00
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_sdr1_sprs(env);
|
|
|
|
register_book3s_207_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* POWER8 Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_ids_sprs(env);
|
|
|
|
register_rmor_sprs(env);
|
|
|
|
register_amr_sprs(env);
|
|
|
|
register_iamr_sprs(env);
|
|
|
|
register_book3s_purr_sprs(env);
|
|
|
|
register_power5p_common_sprs(env);
|
|
|
|
register_power5p_lpar_sprs(env);
|
|
|
|
register_power5p_ear_sprs(env);
|
|
|
|
register_power5p_tb_sprs(env);
|
|
|
|
register_power6_common_sprs(env);
|
|
|
|
register_power6_dbg_sprs(env);
|
|
|
|
register_power8_tce_address_control_sprs(env);
|
|
|
|
register_power8_ids_sprs(env);
|
|
|
|
register_power8_ebb_sprs(env);
|
|
|
|
register_power8_fscr_sprs(env);
|
|
|
|
register_power8_pmu_sup_sprs(env);
|
|
|
|
register_power8_pmu_user_sprs(env);
|
|
|
|
register_power8_tm_sprs(env);
|
|
|
|
register_power8_pspb_sprs(env);
|
|
|
|
register_power8_dpdes_sprs(env);
|
|
|
|
register_vtb_sprs(env);
|
|
|
|
register_power8_ic_sprs(env);
|
|
|
|
register_power8_book4_sprs(env);
|
|
|
|
register_power8_rpr_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* env variables */
|
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
|
|
|
|
|
|
|
/* Allocate hardware IRQ controller */
|
|
|
|
init_excp_POWER8(env);
|
2019-03-23 03:07:57 +01:00
|
|
|
ppcPOWER7_irq_init(env_archcpu(env));
|
2014-02-10 18:26:54 +01:00
|
|
|
}
|
|
|
|
|
2014-07-03 16:48:55 +02:00
|
|
|
static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
|
|
|
|
{
|
2016-03-03 01:08:19 +01:00
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
2014-07-03 16:48:55 +02:00
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-21 23:48:55 +02:00
|
|
|
static bool cpu_has_work_POWER8(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (cs->halted) {
|
|
|
|
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-30 16:30:18 +02:00
|
|
|
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
|
2013-07-04 08:42:32 +02:00
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
2016-06-21 23:48:55 +02:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-07-04 08:42:32 +02:00
|
|
|
|
2013-10-15 18:33:36 +02:00
|
|
|
dc->fw_name = "PowerPC,POWER8";
|
2014-06-30 16:30:18 +02:00
|
|
|
dc->desc = "POWER8";
|
2014-07-03 16:48:55 +02:00
|
|
|
pcc->pvr_match = ppc_pvr_match_power8;
|
2016-06-07 17:39:37 +02:00
|
|
|
pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
|
|
|
|
pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
|
2014-02-10 18:26:54 +01:00
|
|
|
pcc->init_proc = init_proc_POWER8;
|
2013-07-04 08:42:32 +02:00
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2016-06-21 23:48:55 +02:00
|
|
|
cc->has_work = cpu_has_work_POWER8;
|
2014-03-25 03:40:27 +01:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
|
2013-07-04 08:42:32 +02:00
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
2014-01-07 17:06:09 +01:00
|
|
|
PPC_FLOAT_FRSQRTES |
|
2013-07-04 08:42:32 +02:00
|
|
|
PPC_FLOAT_STFIWX |
|
2014-01-07 17:06:05 +01:00
|
|
|
PPC_FLOAT_EXT |
|
2013-07-04 08:42:32 +02:00
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
|
2016-05-03 18:03:34 +02:00
|
|
|
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
|
2013-07-04 08:42:32 +02:00
|
|
|
PPC_SEGMENT_64B | PPC_SLBI |
|
2016-06-21 23:48:52 +02:00
|
|
|
PPC_POPCNTB | PPC_POPCNTWD |
|
|
|
|
PPC_CILDST;
|
2014-01-07 17:05:49 +01:00
|
|
|
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
|
2014-01-07 17:05:55 +01:00
|
|
|
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
|
2014-01-07 17:06:06 +01:00
|
|
|
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
|
2014-02-10 18:26:56 +01:00
|
|
|
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
|
2014-03-07 05:37:39 +01:00
|
|
|
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
|
2014-12-18 17:34:32 +01:00
|
|
|
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
|
2016-06-21 23:48:55 +02:00
|
|
|
PPC2_TM | PPC2_PM_ISA206;
|
2014-04-15 19:21:12 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
2019-12-11 07:07:44 +01:00
|
|
|
(1ull << MSR_HV) |
|
2014-06-04 14:50:59 +02:00
|
|
|
(1ull << MSR_TM) |
|
2014-04-15 19:21:12 +02:00
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_VSX) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
2018-03-05 11:53:48 +01:00
|
|
|
(1ull << MSR_TS0) |
|
|
|
|
(1ull << MSR_TS1) |
|
2014-04-15 19:21:12 +02:00
|
|
|
(1ull << MSR_LE);
|
2020-01-06 06:35:10 +01:00
|
|
|
pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
|
|
|
|
LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
|
|
|
|
LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
|
|
|
|
LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
|
|
|
|
LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
|
|
|
|
pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
|
|
|
|
LPCR_P8_PECE3 | LPCR_P8_PECE4;
|
2015-10-22 09:30:58 +02:00
|
|
|
pcc->mmu_model = POWERPC_MMU_2_07;
|
2013-07-04 08:42:32 +02:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
|
2018-03-23 03:31:52 +01:00
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
|
2019-03-01 03:43:15 +01:00
|
|
|
pcc->lrg_decr_bits = 32;
|
2019-08-27 06:57:51 +02:00
|
|
|
pcc->n_host_threads = 8;
|
2016-07-26 13:58:24 +02:00
|
|
|
#endif
|
|
|
|
pcc->excp_model = POWERPC_EXCP_POWER8;
|
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
|
|
|
|
POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
|
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x8000;
|
|
|
|
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
|
|
|
|
}
|
2017-03-01 07:54:37 +01:00
|
|
|
|
2017-03-29 07:43:45 +02:00
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
|
|
/*
|
|
|
|
* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
|
|
|
|
* Encoded as array of int_32s in the form:
|
|
|
|
* 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
|
|
|
|
* x -> AP encoding
|
|
|
|
* y -> radix mode supported page size (encoded as a shift)
|
|
|
|
*/
|
|
|
|
static struct ppc_radix_page_info POWER9_radix_page_info = {
|
|
|
|
.count = 4,
|
|
|
|
.entries = {
|
|
|
|
0x0000000c, /* 4K - enc: 0x0 */
|
|
|
|
0xa0000010, /* 64K - enc: 0x5 */
|
|
|
|
0x20000015, /* 2M - enc: 0x1 */
|
|
|
|
0x4000001e /* 1G - enc: 0x2 */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
#endif /* CONFIG_SOFTMMU */
|
|
|
|
|
2016-07-26 13:58:24 +02:00
|
|
|
static void init_proc_POWER9(CPUPPCState *env)
|
|
|
|
{
|
2017-03-01 07:54:37 +01:00
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_207_dbg_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
|
|
|
/* POWER8 Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_ids_sprs(env);
|
|
|
|
register_amr_sprs(env);
|
|
|
|
register_iamr_sprs(env);
|
|
|
|
register_book3s_purr_sprs(env);
|
|
|
|
register_power5p_common_sprs(env);
|
|
|
|
register_power5p_lpar_sprs(env);
|
|
|
|
register_power5p_ear_sprs(env);
|
|
|
|
register_power5p_tb_sprs(env);
|
|
|
|
register_power6_common_sprs(env);
|
|
|
|
register_power6_dbg_sprs(env);
|
|
|
|
register_power8_tce_address_control_sprs(env);
|
|
|
|
register_power8_ids_sprs(env);
|
|
|
|
register_power8_ebb_sprs(env);
|
|
|
|
register_power8_fscr_sprs(env);
|
|
|
|
register_power8_pmu_sup_sprs(env);
|
|
|
|
register_power8_pmu_user_sprs(env);
|
|
|
|
register_power8_tm_sprs(env);
|
|
|
|
register_power8_pspb_sprs(env);
|
|
|
|
register_power8_dpdes_sprs(env);
|
|
|
|
register_vtb_sprs(env);
|
|
|
|
register_power8_ic_sprs(env);
|
|
|
|
register_power8_book4_sprs(env);
|
|
|
|
register_power8_rpr_sprs(env);
|
|
|
|
register_power9_mmu_sprs(env);
|
2017-03-01 07:54:37 +01:00
|
|
|
|
2017-08-08 05:42:53 +02:00
|
|
|
/* POWER9 Specific registers */
|
|
|
|
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
|
|
|
|
spr_read_generic, spr_write_generic,
|
|
|
|
KVM_REG_PPC_TIDR, 0);
|
|
|
|
|
2017-08-08 07:09:35 +02:00
|
|
|
/* FIXME: Filter fields properly based on privilege level */
|
|
|
|
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
|
|
|
|
spr_read_generic, spr_write_generic,
|
|
|
|
KVM_REG_PPC_PSSCR, 0);
|
|
|
|
|
2017-03-01 07:54:37 +01:00
|
|
|
/* env variables */
|
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
|
|
|
|
|
|
|
/* Allocate hardware IRQ controller */
|
2019-02-15 17:16:46 +01:00
|
|
|
init_excp_POWER9(env);
|
2019-03-23 03:07:57 +01:00
|
|
|
ppcPOWER9_irq_init(env_archcpu(env));
|
2016-07-26 13:58:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
|
|
|
|
{
|
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-03-01 07:54:40 +01:00
|
|
|
static bool cpu_has_work_POWER9(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (cs->halted) {
|
2019-02-15 17:16:41 +01:00
|
|
|
uint64_t psscr = env->spr[SPR_PSSCR];
|
|
|
|
|
2017-03-01 07:54:40 +01:00
|
|
|
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
|
|
|
|
return false;
|
|
|
|
}
|
2019-02-15 17:16:41 +01:00
|
|
|
|
|
|
|
/* If EC is clear, just return true on any pending interrupt */
|
|
|
|
if (!(psscr & PSSCR_EC)) {
|
|
|
|
return true;
|
|
|
|
}
|
2017-03-01 07:54:40 +01:00
|
|
|
/* External Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_EEE)) {
|
2019-02-15 17:16:48 +01:00
|
|
|
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
|
|
|
|
if (heic == 0 || !msr_hv || msr_pr) {
|
|
|
|
return true;
|
|
|
|
}
|
2017-03-01 07:54:40 +01:00
|
|
|
}
|
|
|
|
/* Decrementer Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_DEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Machine Check or Hypervisor Maintenance Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
|
|
|
|
1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Privileged Doorbell Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_PDEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Hypervisor Doorbell Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_HDEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
2019-02-15 17:16:46 +01:00
|
|
|
/* Hypervisor virtualization exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_HVEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
2017-03-01 07:54:40 +01:00
|
|
|
if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-26 13:58:24 +02:00
|
|
|
POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
2017-03-01 07:54:40 +01:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2016-07-26 13:58:24 +02:00
|
|
|
|
|
|
|
dc->fw_name = "PowerPC,POWER9";
|
|
|
|
dc->desc = "POWER9";
|
|
|
|
pcc->pvr_match = ppc_pvr_match_power9;
|
|
|
|
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
|
2017-01-13 07:28:09 +01:00
|
|
|
pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
|
|
|
|
PCR_COMPAT_2_05;
|
2016-07-26 13:58:24 +02:00
|
|
|
pcc->init_proc = init_proc_POWER9;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
2017-03-01 07:54:40 +01:00
|
|
|
cc->has_work = cpu_has_work_POWER9;
|
2016-07-26 13:58:24 +02:00
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_FRSQRTES |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_FLOAT_EXT |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
2017-05-02 08:37:16 +02:00
|
|
|
PPC_MEM_TLBSYNC |
|
2019-03-07 23:35:48 +01:00
|
|
|
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
|
2016-07-26 13:58:24 +02:00
|
|
|
PPC_SEGMENT_64B | PPC_SLBI |
|
|
|
|
PPC_POPCNTB | PPC_POPCNTWD |
|
|
|
|
PPC_CILDST;
|
|
|
|
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
|
|
|
|
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
|
|
|
|
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
|
|
|
|
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
|
|
|
|
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
|
|
|
|
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
|
2019-01-28 10:46:18 +01:00
|
|
|
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
|
2016-07-26 13:58:24 +02:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
2019-12-11 07:07:44 +01:00
|
|
|
(1ull << MSR_HV) |
|
2016-07-26 13:58:24 +02:00
|
|
|
(1ull << MSR_TM) |
|
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_VSX) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2020-01-06 06:35:10 +01:00
|
|
|
pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
|
|
|
|
(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
|
|
|
|
LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
|
|
|
|
(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
|
|
|
|
LPCR_DEE | LPCR_OEE))
|
|
|
|
| LPCR_MER | LPCR_GTSE | LPCR_TC |
|
|
|
|
LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
|
|
|
|
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
|
2017-02-10 06:25:51 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_3_00;
|
2016-07-26 13:58:24 +02:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
2017-03-01 07:54:38 +01:00
|
|
|
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
|
2016-07-26 13:58:24 +02:00
|
|
|
/* segment page size remain the same */
|
2018-03-23 03:31:52 +01:00
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
|
2017-03-29 07:43:45 +02:00
|
|
|
pcc->radix_page_info = &POWER9_radix_page_info;
|
2019-03-01 03:43:15 +01:00
|
|
|
pcc->lrg_decr_bits = 56;
|
2019-08-27 06:57:51 +02:00
|
|
|
pcc->n_host_threads = 4;
|
2013-07-04 08:42:32 +02:00
|
|
|
#endif
|
2019-02-15 17:16:44 +01:00
|
|
|
pcc->excp_model = POWERPC_EXCP_POWER9;
|
2019-02-15 17:16:47 +01:00
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
|
2013-07-04 08:42:32 +02:00
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
2013-10-22 13:05:46 +02:00
|
|
|
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
|
2020-05-07 13:53:28 +02:00
|
|
|
POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
|
2013-07-04 08:42:32 +02:00
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x8000;
|
2014-05-19 19:59:05 +02:00
|
|
|
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
|
2013-07-04 08:42:32 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
|
2019-12-05 19:44:50 +01:00
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
|
|
/*
|
|
|
|
* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
|
|
|
|
* Encoded as array of int_32s in the form:
|
|
|
|
* 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
|
|
|
|
* x -> AP encoding
|
|
|
|
* y -> radix mode supported page size (encoded as a shift)
|
|
|
|
*/
|
|
|
|
static struct ppc_radix_page_info POWER10_radix_page_info = {
|
|
|
|
.count = 4,
|
|
|
|
.entries = {
|
|
|
|
0x0000000c, /* 4K - enc: 0x0 */
|
|
|
|
0xa0000010, /* 64K - enc: 0x5 */
|
|
|
|
0x20000015, /* 2M - enc: 0x1 */
|
|
|
|
0x4000001e /* 1G - enc: 0x2 */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
#endif /* CONFIG_SOFTMMU */
|
|
|
|
|
|
|
|
static void init_proc_POWER10(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
/* Common Registers */
|
|
|
|
init_proc_book3s_common(env);
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_207_dbg_sprs(env);
|
2019-12-05 19:44:50 +01:00
|
|
|
|
|
|
|
/* POWER8 Specific Registers */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_book3s_ids_sprs(env);
|
|
|
|
register_amr_sprs(env);
|
|
|
|
register_iamr_sprs(env);
|
|
|
|
register_book3s_purr_sprs(env);
|
|
|
|
register_power5p_common_sprs(env);
|
|
|
|
register_power5p_lpar_sprs(env);
|
|
|
|
register_power5p_ear_sprs(env);
|
|
|
|
register_power6_common_sprs(env);
|
|
|
|
register_power6_dbg_sprs(env);
|
|
|
|
register_power8_tce_address_control_sprs(env);
|
|
|
|
register_power8_ids_sprs(env);
|
|
|
|
register_power8_ebb_sprs(env);
|
|
|
|
register_power8_fscr_sprs(env);
|
|
|
|
register_power8_pmu_sup_sprs(env);
|
|
|
|
register_power8_pmu_user_sprs(env);
|
|
|
|
register_power8_tm_sprs(env);
|
|
|
|
register_power8_pspb_sprs(env);
|
|
|
|
register_vtb_sprs(env);
|
|
|
|
register_power8_ic_sprs(env);
|
|
|
|
register_power8_book4_sprs(env);
|
|
|
|
register_power8_rpr_sprs(env);
|
|
|
|
register_power9_mmu_sprs(env);
|
2019-12-05 19:44:50 +01:00
|
|
|
|
|
|
|
/* FIXME: Filter fields properly based on privilege level */
|
|
|
|
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
|
|
|
|
spr_read_generic, spr_write_generic,
|
|
|
|
KVM_REG_PPC_PSSCR, 0);
|
|
|
|
|
|
|
|
/* env variables */
|
|
|
|
env->dcache_line_size = 128;
|
|
|
|
env->icache_line_size = 128;
|
|
|
|
|
|
|
|
/* Allocate hardware IRQ controller */
|
|
|
|
init_excp_POWER10(env);
|
|
|
|
ppcPOWER9_irq_init(env_archcpu(env));
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
|
|
|
|
{
|
|
|
|
if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cpu_has_work_POWER10(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (cs->halted) {
|
|
|
|
uint64_t psscr = env->spr[SPR_PSSCR];
|
|
|
|
|
|
|
|
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If EC is clear, just return true on any pending interrupt */
|
|
|
|
if (!(psscr & PSSCR_EC)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* External Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_EEE)) {
|
|
|
|
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
|
|
|
|
if (heic == 0 || !msr_hv || msr_pr) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Decrementer Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_DEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Machine Check or Hypervisor Maintenance Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
|
|
|
|
1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Privileged Doorbell Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_PDEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Hypervisor Doorbell Exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_HDEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* Hypervisor virtualization exception */
|
|
|
|
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
|
|
|
|
(env->spr[SPR_LPCR] & LPCR_HVEE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
|
|
|
|
dc->fw_name = "PowerPC,POWER10";
|
|
|
|
dc->desc = "POWER10";
|
|
|
|
pcc->pvr_match = ppc_pvr_match_power10;
|
|
|
|
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
|
|
|
|
PCR_COMPAT_3_00;
|
|
|
|
pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
|
|
|
|
PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
|
|
|
|
pcc->init_proc = init_proc_POWER10;
|
|
|
|
pcc->check_pow = check_pow_nocheck;
|
|
|
|
cc->has_work = cpu_has_work_POWER10;
|
|
|
|
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
|
|
|
|
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
|
|
|
|
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
|
|
|
|
PPC_FLOAT_FRSQRTES |
|
|
|
|
PPC_FLOAT_STFIWX |
|
|
|
|
PPC_FLOAT_EXT |
|
|
|
|
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
|
|
|
|
PPC_MEM_SYNC | PPC_MEM_EIEIO |
|
|
|
|
PPC_MEM_TLBSYNC |
|
|
|
|
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
|
|
|
|
PPC_SEGMENT_64B | PPC_SLBI |
|
|
|
|
PPC_POPCNTB | PPC_POPCNTWD |
|
|
|
|
PPC_CILDST;
|
|
|
|
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
|
|
|
|
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
|
|
|
|
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
|
|
|
|
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
|
|
|
|
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
|
|
|
|
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
|
2020-07-02 01:43:37 +02:00
|
|
|
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
|
2019-12-05 19:44:50 +01:00
|
|
|
pcc->msr_mask = (1ull << MSR_SF) |
|
2019-12-11 07:07:44 +01:00
|
|
|
(1ull << MSR_HV) |
|
2019-12-05 19:44:50 +01:00
|
|
|
(1ull << MSR_TM) |
|
|
|
|
(1ull << MSR_VR) |
|
|
|
|
(1ull << MSR_VSX) |
|
|
|
|
(1ull << MSR_EE) |
|
|
|
|
(1ull << MSR_PR) |
|
|
|
|
(1ull << MSR_FP) |
|
|
|
|
(1ull << MSR_ME) |
|
|
|
|
(1ull << MSR_FE0) |
|
|
|
|
(1ull << MSR_SE) |
|
|
|
|
(1ull << MSR_DE) |
|
|
|
|
(1ull << MSR_FE1) |
|
|
|
|
(1ull << MSR_IR) |
|
|
|
|
(1ull << MSR_DR) |
|
|
|
|
(1ull << MSR_PMM) |
|
|
|
|
(1ull << MSR_RI) |
|
|
|
|
(1ull << MSR_LE);
|
2020-01-06 06:35:10 +01:00
|
|
|
pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
|
|
|
|
(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
|
|
|
|
LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
|
|
|
|
(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
|
|
|
|
LPCR_DEE | LPCR_OEE))
|
|
|
|
| LPCR_MER | LPCR_GTSE | LPCR_TC |
|
|
|
|
LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
|
|
|
|
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
|
2019-12-05 19:44:50 +01:00
|
|
|
pcc->mmu_model = POWERPC_MMU_3_00;
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
|
|
|
|
/* segment page size remain the same */
|
|
|
|
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
|
|
|
|
pcc->radix_page_info = &POWER10_radix_page_info;
|
|
|
|
pcc->lrg_decr_bits = 56;
|
|
|
|
#endif
|
2021-05-01 09:24:35 +02:00
|
|
|
pcc->excp_model = POWERPC_EXCP_POWER10;
|
2019-12-05 19:44:50 +01:00
|
|
|
pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
|
|
|
|
pcc->bfd_mach = bfd_mach_ppc64;
|
|
|
|
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
|
|
|
|
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
|
|
|
|
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
|
2021-04-15 07:42:25 +02:00
|
|
|
POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
|
2019-12-05 19:44:50 +01:00
|
|
|
pcc->l1_dcache_size = 0x8000;
|
|
|
|
pcc->l1_icache_size = 0x8000;
|
|
|
|
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
|
|
|
|
}
|
|
|
|
|
2016-03-21 13:52:34 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2018-04-05 08:02:51 +02:00
|
|
|
void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
|
2016-03-21 13:52:34 +01:00
|
|
|
{
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
2017-02-20 00:47:09 +01:00
|
|
|
cpu->vhyp = vhyp;
|
|
|
|
|
2018-04-13 06:54:34 +02:00
|
|
|
/*
|
|
|
|
* With a virtual hypervisor mode we never allow the CPU to go
|
|
|
|
* hypervisor mode itself
|
2016-03-21 13:52:34 +01:00
|
|
|
*/
|
2018-04-13 06:54:34 +02:00
|
|
|
env->msr_mask &= ~MSR_HVB;
|
2016-03-21 13:52:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2017-04-20 03:05:26 +02:00
|
|
|
#endif /* defined(TARGET_PPC64) */
|
2013-02-18 00:16:04 +01:00
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/*****************************************************************************/
|
2011-04-28 17:20:36 +02:00
|
|
|
/* Generic CPU instantiation routine */
|
2013-02-18 00:16:41 +01:00
|
|
|
static void init_ppc_proc(PowerPCCPU *cpu)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2013-02-18 00:16:41 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-09-29 15:06:16 +02:00
|
|
|
int i;
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
env->irq_inputs = NULL;
|
2007-09-29 15:06:16 +02:00
|
|
|
/* Set all exception vectors to an invalid address */
|
2019-03-21 12:45:46 +01:00
|
|
|
for (i = 0; i < POWERPC_EXCP_NB; i++) {
|
2007-09-29 15:06:16 +02:00
|
|
|
env->excp_vectors[i] = (target_ulong)(-1ULL);
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
2007-09-29 15:06:16 +02:00
|
|
|
env->ivor_mask = 0x00000000;
|
|
|
|
env->ivpr_mask = 0x00000000;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Default MMU definitions */
|
|
|
|
env->nb_BATs = 0;
|
|
|
|
env->nb_tlb = 0;
|
|
|
|
env->nb_ways = 0;
|
2011-06-17 01:00:28 +02:00
|
|
|
env->tlb_type = TLB_NONE;
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Register SPR common to all PowerPC implementations */
|
2021-05-05 17:53:07 +02:00
|
|
|
register_generic_sprs(env);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
spr_register(env, SPR_PVR, "PVR",
|
2009-06-05 03:45:03 +02:00
|
|
|
/* Linux permits userspace to read PVR */
|
|
|
|
#if defined(CONFIG_LINUX_USER)
|
|
|
|
&spr_read_generic,
|
|
|
|
#else
|
|
|
|
SPR_NOACCESS,
|
|
|
|
#endif
|
|
|
|
SPR_NOACCESS,
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2013-02-18 00:16:41 +01:00
|
|
|
pcc->pvr);
|
2007-11-18 00:02:20 +01:00
|
|
|
/* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
|
2013-02-18 00:16:41 +01:00
|
|
|
if (pcc->svr != POWERPC_SVR_NONE) {
|
|
|
|
if (pcc->svr & POWERPC_SVR_E500) {
|
2007-11-18 00:02:20 +01:00
|
|
|
spr_register(env, SPR_E500_SVR, "SVR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2013-02-18 00:16:41 +01:00
|
|
|
pcc->svr & ~POWERPC_SVR_E500);
|
2007-11-18 00:02:20 +01:00
|
|
|
} else {
|
|
|
|
spr_register(env, SPR_SVR, "SVR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
2013-02-18 00:16:41 +01:00
|
|
|
pcc->svr);
|
2007-11-18 00:02:20 +01:00
|
|
|
}
|
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
|
2013-02-18 00:16:41 +01:00
|
|
|
(*pcc->init_proc)(env);
|
2013-03-29 03:06:27 +01:00
|
|
|
|
2019-02-06 17:51:33 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
ppc_gdb_gen_spr_xml(cpu);
|
|
|
|
#endif
|
|
|
|
|
2007-10-08 04:58:07 +02:00
|
|
|
/* MSR bits & flags consistency checks */
|
|
|
|
if (env->msr_mask & (1 << 25)) {
|
|
|
|
switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
|
|
|
|
case POWERPC_FLAG_SPE:
|
|
|
|
case POWERPC_FLAG_VRE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (env->msr_mask & (1 << 17)) {
|
|
|
|
switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
|
|
|
|
case POWERPC_FLAG_TGPR:
|
|
|
|
case POWERPC_FLAG_CE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (env->msr_mask & (1 << 10)) {
|
|
|
|
switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_UBLE)) {
|
|
|
|
case POWERPC_FLAG_SE:
|
|
|
|
case POWERPC_FLAG_DWE:
|
|
|
|
case POWERPC_FLAG_UBLE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
|
|
|
|
"POWERPC_FLAG_UBLE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
|
|
|
|
POWERPC_FLAG_UBLE)) {
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
|
|
|
|
"POWERPC_FLAG_UBLE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (env->msr_mask & (1 << 9)) {
|
|
|
|
switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
|
|
|
|
case POWERPC_FLAG_BE:
|
|
|
|
case POWERPC_FLAG_DE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
if (env->msr_mask & (1 << 2)) {
|
|
|
|
switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
|
|
|
|
case POWERPC_FLAG_PX:
|
|
|
|
case POWERPC_FLAG_PMM:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
|
|
|
|
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
|
|
|
"Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2007-11-19 02:48:12 +01:00
|
|
|
if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
|
|
|
|
fprintf(stderr, "PowerPC flags inconsistency\n"
|
|
|
|
"Should define the time-base and decrementer clock source\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Allocate TLBs buffer when needed */
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
if (env->nb_tlb != 0) {
|
|
|
|
int nb_tlb = env->nb_tlb;
|
2019-03-21 12:45:46 +01:00
|
|
|
if (env->id_tlbs != 0) {
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
nb_tlb *= 2;
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
2011-06-17 01:00:28 +02:00
|
|
|
switch (env->tlb_type) {
|
|
|
|
case TLB_6XX:
|
2018-11-27 14:05:06 +01:00
|
|
|
env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
|
2011-06-17 01:00:28 +02:00
|
|
|
break;
|
|
|
|
case TLB_EMB:
|
2018-11-27 14:05:06 +01:00
|
|
|
env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
|
2011-06-17 01:00:28 +02:00
|
|
|
break;
|
|
|
|
case TLB_MAS:
|
2018-11-27 14:05:06 +01:00
|
|
|
env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
|
2011-06-17 01:00:28 +02:00
|
|
|
break;
|
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* Pre-compute some useful values */
|
|
|
|
env->tlb_per_way = env->nb_tlb / env->nb_ways;
|
|
|
|
}
|
|
|
|
if (env->irq_inputs == NULL) {
|
2017-09-11 21:52:53 +02:00
|
|
|
warn_report("no internal IRQ controller registered."
|
|
|
|
" Attempt QEMU to crash very soon !");
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
#endif
|
2007-10-26 01:14:50 +02:00
|
|
|
if (env->check_pow == NULL) {
|
2017-09-11 21:52:56 +02:00
|
|
|
warn_report("no power management check handler registered."
|
2017-09-11 21:52:53 +02:00
|
|
|
" Attempt QEMU to crash very soon !");
|
2007-10-26 01:14:50 +02:00
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(PPC_DUMP_CPU)
|
2017-04-20 03:05:26 +02:00
|
|
|
static void dump_ppc_sprs(CPUPPCState *env)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
|
|
|
ppc_spr_t *spr;
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
uint32_t sr, sw;
|
|
|
|
#endif
|
|
|
|
uint32_t ur, uw;
|
|
|
|
int i, j, n;
|
|
|
|
|
|
|
|
printf("Special purpose registers:\n");
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
for (j = 0; j < 32; j++) {
|
|
|
|
n = (i << 5) | j;
|
|
|
|
spr = &env->spr_cb[n];
|
|
|
|
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
|
|
|
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
|
|
|
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
|
|
|
if (sw || sr || uw || ur) {
|
|
|
|
printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
|
|
|
|
(i << 5) | j, (i << 5) | j, spr->name,
|
|
|
|
sw ? 'w' : '-', sr ? 'r' : '-',
|
|
|
|
uw ? 'w' : '-', ur ? 'r' : '-');
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (uw || ur) {
|
|
|
|
printf("SPR: %4d (%03x) %-8s u%c%c\n",
|
|
|
|
(i << 5) | j, (i << 5) | j, spr->name,
|
|
|
|
uw ? 'w' : '-', ur ? 'r' : '-');
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
fflush(stdout);
|
|
|
|
fflush(stderr);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-03-21 05:30:13 +01:00
|
|
|
static void ppc_cpu_realize(DeviceState *dev, Error **errp)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
{
|
2013-06-28 21:27:39 +02:00
|
|
|
CPUState *cs = CPU(dev);
|
2013-01-16 03:55:14 +01:00
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(dev);
|
2013-01-06 09:31:30 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
|
|
Error *local_err = NULL;
|
2013-01-23 18:20:38 +01:00
|
|
|
|
2016-10-20 13:26:03 +02:00
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
2015-06-24 04:31:14 +02:00
|
|
|
if (local_err != NULL) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2017-08-31 08:38:46 +02:00
|
|
|
if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
|
|
|
|
cpu->vcpu_id = cs->cpu_index;
|
2016-04-26 15:41:04 +02:00
|
|
|
}
|
ppc64: Rudimentary Support for extra page sizes on server CPUs
More recent Power server chips (i.e. based on the 64 bit hash MMU)
support more than just the traditional 4k and 16M page sizes. This
can get quite complicated, because which page sizes are supported,
which combinations are supported within an MMU segment and how these
page sizes are encoded both in the SLB entry and the hash PTE can vary
depending on the CPU model (they are not specified by the
architecture). In addition the firmware or hypervisor may not permit
use of certain page sizes, for various reasons. Whether various page
sizes are supported on KVM, for example, depends on whether the PR or
HV variant of KVM is in use, and on the page size of the memory
backing the guest's RAM.
This patch adds information to the CPUState and cpu defs to describe
the supported page sizes and encodings. Since TCG does not yet
support any extended page sizes, we just set this to NULL in the
static CPU definitions, expanding this to the default 4k and 16M page
sizes when we initialize the cpu state. When using KVM, however, we
instead determine available page sizes using the new
KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use
some defaults, with some guesswork which should do the right thing for
existing HV and PR implementations. The fallback might not be correct
for future versions, but that's ok, because they'll have
KVM_PPC_GET_SMMU_INFO.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-18 21:56:25 +02:00
|
|
|
|
2014-02-01 15:45:51 +01:00
|
|
|
if (tcg_enabled()) {
|
2012-12-17 06:18:02 +01:00
|
|
|
if (ppc_fixup_cpu(cpu) != 0) {
|
2013-01-06 09:31:30 +01:00
|
|
|
error_setg(errp, "Unable to emulate selected CPU with TCG");
|
2017-06-15 07:44:24 +02:00
|
|
|
goto unrealize;
|
2012-04-04 07:02:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
create_ppc_opcodes(cpu, &local_err);
|
|
|
|
if (local_err != NULL) {
|
|
|
|
error_propagate(errp, local_err);
|
2017-06-15 07:44:24 +02:00
|
|
|
goto unrealize;
|
2013-01-06 09:31:30 +01:00
|
|
|
}
|
2013-02-18 00:16:41 +01:00
|
|
|
init_ppc_proc(cpu);
|
2009-01-24 16:08:00 +01:00
|
|
|
|
2021-04-26 20:47:06 +02:00
|
|
|
ppc_gdb_init(cs, pcc);
|
2013-07-27 02:53:25 +02:00
|
|
|
qemu_init_vcpu(cs);
|
|
|
|
|
2013-01-16 03:55:14 +01:00
|
|
|
pcc->parent_realize(dev, errp);
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
#if defined(PPC_DUMP_CPU)
|
2007-04-16 11:31:49 +02:00
|
|
|
{
|
2013-06-28 21:27:39 +02:00
|
|
|
CPUPPCState *env = &cpu->env;
|
2008-09-20 10:07:15 +02:00
|
|
|
const char *mmu_model, *excp_model, *bus_model;
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
switch (env->mmu_model) {
|
|
|
|
case POWERPC_MMU_32B:
|
|
|
|
mmu_model = "PowerPC 32";
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_SOFT_6xx:
|
|
|
|
mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_SOFT_74xx:
|
|
|
|
mmu_model = "PowerPC 74xx with software driven TLBs";
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_SOFT_4xx:
|
|
|
|
mmu_model = "PowerPC 4xx with software driven TLBs";
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_SOFT_4xx_Z:
|
|
|
|
mmu_model = "PowerPC 4xx with software driven TLBs "
|
|
|
|
"and zones protections";
|
|
|
|
break;
|
2007-11-17 23:42:36 +01:00
|
|
|
case POWERPC_MMU_REAL:
|
|
|
|
mmu_model = "PowerPC real mode only";
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_MPC8xx:
|
|
|
|
mmu_model = "PowerPC MPC8xx";
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
break;
|
|
|
|
case POWERPC_MMU_BOOKE:
|
|
|
|
mmu_model = "PowerPC BookE";
|
|
|
|
break;
|
2011-04-30 23:34:58 +02:00
|
|
|
case POWERPC_MMU_BOOKE206:
|
|
|
|
mmu_model = "PowerPC BookE 2.06";
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
break;
|
2007-11-17 23:42:36 +01:00
|
|
|
case POWERPC_MMU_601:
|
|
|
|
mmu_model = "PowerPC 601";
|
|
|
|
break;
|
2017-04-20 03:05:26 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-10-03 03:05:39 +02:00
|
|
|
case POWERPC_MMU_64B:
|
|
|
|
mmu_model = "PowerPC 64";
|
|
|
|
break;
|
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
default:
|
|
|
|
mmu_model = "Unknown or invalid";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (env->excp_model) {
|
|
|
|
case POWERPC_EXCP_STD:
|
|
|
|
excp_model = "PowerPC";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_40x:
|
|
|
|
excp_model = "PowerPC 40x";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_601:
|
|
|
|
excp_model = "PowerPC 601";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_602:
|
|
|
|
excp_model = "PowerPC 602";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_603:
|
|
|
|
excp_model = "PowerPC 603";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_603E:
|
|
|
|
excp_model = "PowerPC 603e";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_604:
|
|
|
|
excp_model = "PowerPC 604";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_7x0:
|
|
|
|
excp_model = "PowerPC 740/750";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_7x5:
|
|
|
|
excp_model = "PowerPC 745/755";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_74xx:
|
|
|
|
excp_model = "PowerPC 74xx";
|
|
|
|
break;
|
|
|
|
case POWERPC_EXCP_BOOKE:
|
|
|
|
excp_model = "PowerPC BookE";
|
|
|
|
break;
|
2017-04-20 03:05:26 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-10-03 03:05:39 +02:00
|
|
|
case POWERPC_EXCP_970:
|
|
|
|
excp_model = "PowerPC 970";
|
|
|
|
break;
|
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
default:
|
|
|
|
excp_model = "Unknown or invalid";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (env->bus_model) {
|
|
|
|
case PPC_FLAGS_INPUT_6xx:
|
|
|
|
bus_model = "PowerPC 6xx";
|
|
|
|
break;
|
|
|
|
case PPC_FLAGS_INPUT_BookE:
|
|
|
|
bus_model = "PowerPC BookE";
|
|
|
|
break;
|
|
|
|
case PPC_FLAGS_INPUT_405:
|
|
|
|
bus_model = "PowerPC 405";
|
|
|
|
break;
|
|
|
|
case PPC_FLAGS_INPUT_401:
|
|
|
|
bus_model = "PowerPC 401/403";
|
|
|
|
break;
|
2007-11-17 23:42:36 +01:00
|
|
|
case PPC_FLAGS_INPUT_RCPU:
|
|
|
|
bus_model = "RCPU / MPC8xx";
|
|
|
|
break;
|
2017-04-20 03:05:26 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-10-03 03:05:39 +02:00
|
|
|
case PPC_FLAGS_INPUT_970:
|
|
|
|
bus_model = "PowerPC 970";
|
|
|
|
break;
|
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
default:
|
|
|
|
bus_model = "Unknown or invalid";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
|
|
|
|
" MMU model : %s\n",
|
2013-12-20 03:14:57 +01:00
|
|
|
object_class_get_name(OBJECT_CLASS(pcc)),
|
|
|
|
pcc->pvr, pcc->msr_mask, mmu_model);
|
2007-10-07 17:43:50 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2013-12-20 03:14:57 +01:00
|
|
|
if (env->tlb.tlb6) {
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
printf(" %d %s TLB in %d ways\n",
|
|
|
|
env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
|
|
|
|
env->nb_ways);
|
|
|
|
}
|
2007-10-07 17:43:50 +02:00
|
|
|
#endif
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
printf(" Exceptions model : %s\n"
|
|
|
|
" Bus model : %s\n",
|
|
|
|
excp_model, bus_model);
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" MSR features :\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
if (env->flags & POWERPC_FLAG_SPE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" signal processing engine enable"
|
|
|
|
"\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_VRE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" vector processor enable\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
|
|
|
if (env->flags & POWERPC_FLAG_TGPR) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" temporary GPRs\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_CE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" critical input enable\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
|
|
|
if (env->flags & POWERPC_FLAG_SE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" single-step trace mode\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_DWE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" debug wait enable\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_UBLE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" user BTB lock enable\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
|
|
|
if (env->flags & POWERPC_FLAG_BE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" branch-step trace mode\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_DE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" debug interrupt enable\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
|
|
|
if (env->flags & POWERPC_FLAG_PX) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" inclusive protection\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
} else if (env->flags & POWERPC_FLAG_PMM) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" performance monitor mark\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
|
|
|
if (env->flags == POWERPC_FLAG_NONE) {
|
2007-10-08 04:58:07 +02:00
|
|
|
printf(" none\n");
|
2019-03-21 12:45:46 +01:00
|
|
|
}
|
2007-11-19 02:48:12 +01:00
|
|
|
printf(" Time-base/decrementer clock source: %s\n",
|
|
|
|
env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
|
2013-06-28 21:27:39 +02:00
|
|
|
dump_ppc_insns(env);
|
|
|
|
dump_ppc_sprs(env);
|
|
|
|
fflush(stdout);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
2007-04-16 11:31:49 +02:00
|
|
|
#endif
|
2017-06-15 07:44:24 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
unrealize:
|
|
|
|
cpu_exec_unrealizefn(cs);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
2005-07-02 22:59:34 +02:00
|
|
|
|
qdev: Unrealize must not fail
Devices may have component devices and buses.
Device realization may fail. Realization is recursive: a device's
realize() method realizes its components, and device_set_realized()
realizes its buses (which should in turn realize the devices on that
bus, except bus_set_realized() doesn't implement that, yet).
When realization of a component or bus fails, we need to roll back:
unrealize everything we realized so far. If any of these unrealizes
failed, the device would be left in an inconsistent state. Must not
happen.
device_set_realized() lets it happen: it ignores errors in the roll
back code starting at label child_realize_fail.
Since realization is recursive, unrealization must be recursive, too.
But how could a partly failed unrealize be rolled back? We'd have to
re-realize, which can fail. This design is fundamentally broken.
device_set_realized() does not roll back at all. Instead, it keeps
unrealizing, ignoring further errors.
It can screw up even for a device with no buses: if the lone
dc->unrealize() fails, it still unregisters vmstate, and calls
listeners' unrealize() callback.
bus_set_realized() does not roll back either. Instead, it stops
unrealizing.
Fortunately, no unrealize method can fail, as we'll see below.
To fix the design error, drop parameter @errp from all the unrealize
methods.
Any unrealize method that uses @errp now needs an update. This leads
us to unrealize() methods that can fail. Merely passing it to another
unrealize method cannot cause failure, though. Here are the ones that
do other things with @errp:
* virtio_serial_device_unrealize()
Fails when qbus_set_hotplug_handler() fails, but still does all the
other work. On failure, the device would stay realized with its
resources completely gone. Oops. Can't happen, because
qbus_set_hotplug_handler() can't actually fail here. Pass
&error_abort to qbus_set_hotplug_handler() instead.
* hw/ppc/spapr_drc.c's unrealize()
Fails when object_property_del() fails, but all the other work is
already done. On failure, the device would stay realized with its
vmstate registration gone. Oops. Can't happen, because
object_property_del() can't actually fail here. Pass &error_abort
to object_property_del() instead.
* spapr_phb_unrealize()
Fails and bails out when remove_drcs() fails, but other work is
already done. On failure, the device would stay realized with some
of its resources gone. Oops. remove_drcs() fails only when
chassis_from_bus()'s object_property_get_uint() fails, and it can't
here. Pass &error_abort to remove_drcs() instead.
Therefore, no unrealize method can fail before this patch.
device_set_realized()'s recursive unrealization via bus uses
object_property_set_bool(). Can't drop @errp there, so pass
&error_abort.
We similarly unrealize with object_property_set_bool() elsewhere,
always ignoring errors. Pass &error_abort instead.
Several unrealize methods no longer handle errors from other unrealize
methods: virtio_9p_device_unrealize(),
virtio_input_device_unrealize(), scsi_qdev_unrealize(), ...
Much of the deleted error handling looks wrong anyway.
One unrealize methods no longer ignore such errors:
usb_ehci_pci_exit().
Several realize methods no longer ignore errors when rolling back:
v9fs_device_realize_common(), pci_qdev_unrealize(),
spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(),
virtio_device_realize().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-17-armbru@redhat.com>
2020-05-05 17:29:24 +02:00
|
|
|
static void ppc_cpu_unrealize(DeviceState *dev)
|
2013-06-09 22:11:49 +02:00
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(dev);
|
2016-10-20 13:26:04 +02:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
2013-06-09 22:11:49 +02:00
|
|
|
|
qdev: Unrealize must not fail
Devices may have component devices and buses.
Device realization may fail. Realization is recursive: a device's
realize() method realizes its components, and device_set_realized()
realizes its buses (which should in turn realize the devices on that
bus, except bus_set_realized() doesn't implement that, yet).
When realization of a component or bus fails, we need to roll back:
unrealize everything we realized so far. If any of these unrealizes
failed, the device would be left in an inconsistent state. Must not
happen.
device_set_realized() lets it happen: it ignores errors in the roll
back code starting at label child_realize_fail.
Since realization is recursive, unrealization must be recursive, too.
But how could a partly failed unrealize be rolled back? We'd have to
re-realize, which can fail. This design is fundamentally broken.
device_set_realized() does not roll back at all. Instead, it keeps
unrealizing, ignoring further errors.
It can screw up even for a device with no buses: if the lone
dc->unrealize() fails, it still unregisters vmstate, and calls
listeners' unrealize() callback.
bus_set_realized() does not roll back either. Instead, it stops
unrealizing.
Fortunately, no unrealize method can fail, as we'll see below.
To fix the design error, drop parameter @errp from all the unrealize
methods.
Any unrealize method that uses @errp now needs an update. This leads
us to unrealize() methods that can fail. Merely passing it to another
unrealize method cannot cause failure, though. Here are the ones that
do other things with @errp:
* virtio_serial_device_unrealize()
Fails when qbus_set_hotplug_handler() fails, but still does all the
other work. On failure, the device would stay realized with its
resources completely gone. Oops. Can't happen, because
qbus_set_hotplug_handler() can't actually fail here. Pass
&error_abort to qbus_set_hotplug_handler() instead.
* hw/ppc/spapr_drc.c's unrealize()
Fails when object_property_del() fails, but all the other work is
already done. On failure, the device would stay realized with its
vmstate registration gone. Oops. Can't happen, because
object_property_del() can't actually fail here. Pass &error_abort
to object_property_del() instead.
* spapr_phb_unrealize()
Fails and bails out when remove_drcs() fails, but other work is
already done. On failure, the device would stay realized with some
of its resources gone. Oops. remove_drcs() fails only when
chassis_from_bus()'s object_property_get_uint() fails, and it can't
here. Pass &error_abort to remove_drcs() instead.
Therefore, no unrealize method can fail before this patch.
device_set_realized()'s recursive unrealization via bus uses
object_property_set_bool(). Can't drop @errp there, so pass
&error_abort.
We similarly unrealize with object_property_set_bool() elsewhere,
always ignoring errors. Pass &error_abort instead.
Several unrealize methods no longer handle errors from other unrealize
methods: virtio_9p_device_unrealize(),
virtio_input_device_unrealize(), scsi_qdev_unrealize(), ...
Much of the deleted error handling looks wrong anyway.
One unrealize methods no longer ignore such errors:
usb_ehci_pci_exit().
Several realize methods no longer ignore errors when rolling back:
v9fs_device_realize_common(), pci_qdev_unrealize(),
spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(),
virtio_device_realize().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-17-armbru@redhat.com>
2020-05-05 17:29:24 +02:00
|
|
|
pcc->parent_unrealize(dev);
|
2015-06-24 04:31:14 +02:00
|
|
|
|
2020-10-15 23:18:32 +02:00
|
|
|
cpu_remove_sync(CPU(cpu));
|
|
|
|
|
2021-04-29 18:21:24 +02:00
|
|
|
destroy_ppc_opcodes(cpu);
|
2013-06-09 22:11:49 +02:00
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
|
2011-10-18 02:00:51 +02:00
|
|
|
{
|
2013-01-06 09:31:30 +01:00
|
|
|
ObjectClass *oc = (ObjectClass *)a;
|
|
|
|
uint32_t pvr = *(uint32_t *)b;
|
|
|
|
PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
|
|
|
|
|
|
|
|
/* -cpu host does a PVR lookup during construction */
|
|
|
|
if (unlikely(strcmp(object_class_get_name(oc),
|
|
|
|
TYPE_HOST_POWERPC_CPU) == 0)) {
|
|
|
|
return -1;
|
2011-10-18 02:00:51 +02:00
|
|
|
}
|
|
|
|
|
2013-02-18 00:16:41 +01:00
|
|
|
return pcc->pvr == pvr ? 0 : -1;
|
2011-10-18 02:00:51 +02:00
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
2013-01-06 09:31:30 +01:00
|
|
|
GSList *list, *item;
|
|
|
|
PowerPCCPUClass *pcc = NULL;
|
ppc: Remove broken partial PVR matching
The ppc target contains a ppc_find_by_pvr() function, which looks up a
CPU spec based on a PVR (that is, based on the value in the target cpu's
Processor Version Register). PVR values contain information on both the
cpu model (upper 16 bits, usually) and on the precise revision (low 16
bits, usually).
ppc_find_by_pvr, as well as making exact PVR matches, attempts to find
"close" PVR matches, when we don't have a CPU spec for the exact revision
specified. This sounds like a good idea, execpt that the current logic
is completely nonsensical.
It seems to assume CPU families are subdivided bit by bit in the PVR in a
way they just aren't. Specifically, it requires a match on all bits of the
specified pvr up to the last non-zero bit. This has the bizarre effect
that when the low bits are simply a sequential revision number (a common
though not universal pattern), then odd specified revisions must be matched
exactly, whereas even specified revisions will also match the next odd
revision, likewise for powers of 4, 8 and so forth.
To correctly do inexact matching we'd need to re-organize the table of CPU
specs to include a mask showing what PVR range the spec is compatible with
(similar to the cputable code in the Linux kernel).
For now, just remove the bogosity by only permitting exact PVR matches.
That at least makes the matching simple and consistent. If we need inexact
matching we can add the necessary per-subfamily masks later.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-13 00:40:31 +02:00
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
list = object_class_get_list(TYPE_POWERPC_CPU, false);
|
|
|
|
item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
|
|
|
|
if (item != NULL) {
|
|
|
|
pcc = POWERPC_CPU_CLASS(item->data);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
2013-01-06 09:31:30 +01:00
|
|
|
g_slist_free(list);
|
|
|
|
|
|
|
|
return pcc;
|
|
|
|
}
|
|
|
|
|
2013-09-27 10:05:03 +02:00
|
|
|
static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
|
|
|
|
{
|
|
|
|
ObjectClass *oc = (ObjectClass *)a;
|
|
|
|
uint32_t pvr = *(uint32_t *)b;
|
|
|
|
PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
|
|
|
|
|
|
|
|
/* -cpu host does a PVR lookup during construction */
|
|
|
|
if (unlikely(strcmp(object_class_get_name(oc),
|
|
|
|
TYPE_HOST_POWERPC_CPU) == 0)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2014-07-03 16:48:55 +02:00
|
|
|
if (pcc->pvr_match(pcc, pvr)) {
|
|
|
|
return 0;
|
|
|
|
}
|
2013-09-27 10:05:03 +02:00
|
|
|
|
2014-07-03 16:48:55 +02:00
|
|
|
return -1;
|
2013-09-27 10:05:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
|
|
|
|
{
|
|
|
|
GSList *list, *item;
|
|
|
|
PowerPCCPUClass *pcc = NULL;
|
|
|
|
|
|
|
|
list = object_class_get_list(TYPE_POWERPC_CPU, true);
|
|
|
|
item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
|
|
|
|
if (item != NULL) {
|
|
|
|
pcc = POWERPC_CPU_CLASS(item->data);
|
|
|
|
}
|
|
|
|
g_slist_free(list);
|
|
|
|
|
|
|
|
return pcc;
|
|
|
|
}
|
|
|
|
|
2017-10-09 21:51:05 +02:00
|
|
|
static const char *ppc_cpu_lookup_alias(const char *alias)
|
2017-10-09 21:51:04 +02:00
|
|
|
{
|
|
|
|
int ai;
|
|
|
|
|
|
|
|
for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
|
|
|
|
if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
|
|
|
|
return ppc_cpu_aliases[ai].model;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
static ObjectClass *ppc_cpu_class_by_name(const char *name)
|
2007-11-11 00:51:02 +01:00
|
|
|
{
|
2017-08-30 15:24:32 +02:00
|
|
|
char *cpu_model, *typename;
|
|
|
|
ObjectClass *oc;
|
2008-09-20 10:07:15 +02:00
|
|
|
const char *p;
|
2017-08-30 15:24:33 +02:00
|
|
|
unsigned long pvr;
|
|
|
|
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
|
|
|
|
* 0x prefix if present)
|
2017-08-30 15:24:33 +02:00
|
|
|
*/
|
|
|
|
if (!qemu_strtoul(name, &p, 16, &pvr)) {
|
|
|
|
int len = p - name;
|
|
|
|
len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
|
|
|
|
if ((len == 8) && (*p == '\0')) {
|
|
|
|
return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
|
2011-10-18 02:00:51 +02:00
|
|
|
}
|
2013-01-06 09:31:30 +01:00
|
|
|
}
|
2011-10-18 02:00:51 +02:00
|
|
|
|
2017-08-30 15:24:32 +02:00
|
|
|
cpu_model = g_ascii_strdown(name, -1);
|
|
|
|
p = ppc_cpu_lookup_alias(cpu_model);
|
|
|
|
if (p) {
|
|
|
|
g_free(cpu_model);
|
|
|
|
cpu_model = g_strdup(p);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
2007-11-11 00:51:02 +01:00
|
|
|
|
2017-08-30 15:24:32 +02:00
|
|
|
typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
|
|
|
|
oc = object_class_by_name(typename);
|
|
|
|
g_free(typename);
|
|
|
|
g_free(cpu_model);
|
2014-04-11 19:34:26 +02:00
|
|
|
|
2018-08-21 13:27:48 +02:00
|
|
|
return oc;
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
|
|
|
|
2017-05-10 06:19:32 +02:00
|
|
|
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
|
|
|
|
{
|
|
|
|
ObjectClass *oc = OBJECT_CLASS(pcc);
|
|
|
|
|
|
|
|
while (oc && !object_class_is_abstract(oc)) {
|
|
|
|
oc = object_class_get_parent(oc);
|
|
|
|
}
|
|
|
|
assert(oc);
|
|
|
|
|
|
|
|
return POWERPC_CPU_CLASS(oc);
|
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
/* Sort by PVR, ordering special case "host" last. */
|
|
|
|
static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
|
|
|
|
{
|
|
|
|
ObjectClass *oc_a = (ObjectClass *)a;
|
|
|
|
ObjectClass *oc_b = (ObjectClass *)b;
|
|
|
|
PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
|
|
|
|
PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
|
|
|
|
const char *name_a = object_class_get_name(oc_a);
|
|
|
|
const char *name_b = object_class_get_name(oc_b);
|
|
|
|
|
|
|
|
if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
|
|
|
|
return 1;
|
|
|
|
} else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
|
|
|
|
return -1;
|
|
|
|
} else {
|
|
|
|
/* Avoid an integer overflow during subtraction */
|
2013-02-18 00:16:41 +01:00
|
|
|
if (pcc_a->pvr < pcc_b->pvr) {
|
2013-01-06 09:31:30 +01:00
|
|
|
return -1;
|
2013-02-18 00:16:41 +01:00
|
|
|
} else if (pcc_a->pvr > pcc_b->pvr) {
|
2013-01-06 09:31:30 +01:00
|
|
|
return 1;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
|
|
|
|
{
|
|
|
|
ObjectClass *oc = data;
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
2017-05-10 06:19:32 +02:00
|
|
|
DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
|
2013-02-18 00:16:40 +01:00
|
|
|
const char *typename = object_class_get_name(oc);
|
|
|
|
char *name;
|
2013-02-23 08:34:28 +01:00
|
|
|
int i;
|
2013-01-06 09:31:30 +01:00
|
|
|
|
2013-02-23 12:22:12 +01:00
|
|
|
if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
|
|
|
|
return;
|
|
|
|
}
|
2013-02-18 00:16:44 +01:00
|
|
|
|
2013-02-18 00:16:40 +01:00
|
|
|
name = g_strndup(typename,
|
2017-08-30 15:24:29 +02:00
|
|
|
strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
|
2013-02-25 04:43:17 +01:00
|
|
|
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
|
2013-06-22 03:53:35 +02:00
|
|
|
PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
|
2017-08-30 15:24:34 +02:00
|
|
|
ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
|
2013-02-23 08:34:28 +01:00
|
|
|
|
|
|
|
if (alias_oc != oc) {
|
|
|
|
continue;
|
|
|
|
}
|
2017-05-10 06:19:32 +02:00
|
|
|
/*
|
|
|
|
* If running with KVM, we might update the family alias later, so
|
|
|
|
* avoid printing the wrong alias here and use "preferred" instead
|
|
|
|
*/
|
|
|
|
if (strcmp(alias->alias, family->desc) == 0) {
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
|
|
|
|
alias->alias, family->desc);
|
2017-05-10 06:19:32 +02:00
|
|
|
} else {
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("PowerPC %-16s (alias for %s)\n",
|
|
|
|
alias->alias, name);
|
2017-05-10 06:19:32 +02:00
|
|
|
}
|
2013-02-23 08:34:28 +01:00
|
|
|
}
|
2013-02-18 00:16:40 +01:00
|
|
|
g_free(name);
|
2013-01-06 09:31:30 +01:00
|
|
|
}
|
|
|
|
|
2019-04-17 21:17:57 +02:00
|
|
|
void ppc_cpu_list(void)
|
2013-01-06 09:31:30 +01:00
|
|
|
{
|
|
|
|
GSList *list;
|
|
|
|
|
|
|
|
list = object_class_get_list(TYPE_POWERPC_CPU, false);
|
|
|
|
list = g_slist_sort(list, ppc_cpu_list_compare);
|
2019-04-17 21:17:57 +02:00
|
|
|
g_slist_foreach(list, ppc_cpu_list_entry, NULL);
|
2013-01-06 09:31:30 +01:00
|
|
|
g_slist_free(list);
|
2013-02-18 00:16:04 +01:00
|
|
|
|
2013-02-23 12:22:12 +01:00
|
|
|
#ifdef CONFIG_KVM
|
2019-04-17 21:17:57 +02:00
|
|
|
qemu_printf("\n");
|
|
|
|
qemu_printf("PowerPC %-16s\n", "host");
|
2013-02-23 12:22:12 +01:00
|
|
|
#endif
|
2013-01-06 09:31:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
|
|
|
|
{
|
|
|
|
ObjectClass *oc = data;
|
|
|
|
CpuDefinitionInfoList **first = user_data;
|
2013-02-18 00:16:40 +01:00
|
|
|
const char *typename;
|
2013-01-06 09:31:30 +01:00
|
|
|
CpuDefinitionInfo *info;
|
|
|
|
|
2013-02-18 00:16:40 +01:00
|
|
|
typename = object_class_get_name(oc);
|
2013-01-06 09:31:30 +01:00
|
|
|
info = g_malloc0(sizeof(*info));
|
2013-02-18 00:16:40 +01:00
|
|
|
info->name = g_strndup(typename,
|
2017-08-30 15:24:29 +02:00
|
|
|
strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
|
2013-01-06 09:31:30 +01:00
|
|
|
|
2020-11-13 02:13:37 +01:00
|
|
|
QAPI_LIST_PREPEND(*first, info);
|
2005-07-02 22:59:34 +02:00
|
|
|
}
|
2012-04-06 14:39:03 +02:00
|
|
|
|
2019-02-14 16:22:47 +01:00
|
|
|
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
|
2012-08-10 18:04:15 +02:00
|
|
|
{
|
|
|
|
CpuDefinitionInfoList *cpu_list = NULL;
|
2013-01-06 09:31:30 +01:00
|
|
|
GSList *list;
|
2013-02-23 08:52:24 +01:00
|
|
|
int i;
|
2012-08-10 18:04:15 +02:00
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
list = object_class_get_list(TYPE_POWERPC_CPU, false);
|
|
|
|
g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
|
|
|
|
g_slist_free(list);
|
2012-08-10 18:04:15 +02:00
|
|
|
|
2013-02-25 04:43:17 +01:00
|
|
|
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
|
2013-06-22 03:53:35 +02:00
|
|
|
PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
|
2013-02-23 08:52:24 +01:00
|
|
|
ObjectClass *oc;
|
|
|
|
CpuDefinitionInfo *info;
|
|
|
|
|
2017-08-30 15:24:34 +02:00
|
|
|
oc = ppc_cpu_class_by_name(alias->model);
|
2013-02-23 08:52:24 +01:00
|
|
|
if (oc == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
info = g_malloc0(sizeof(*info));
|
|
|
|
info->name = g_strdup(alias->alias);
|
2016-11-16 19:21:39 +01:00
|
|
|
info->q_typename = g_strdup(object_class_get_name(oc));
|
2013-02-23 08:52:24 +01:00
|
|
|
|
2020-11-13 02:13:37 +01:00
|
|
|
QAPI_LIST_PREPEND(cpu_list, info);
|
2013-02-23 08:52:24 +01:00
|
|
|
}
|
|
|
|
|
2013-01-06 09:31:30 +01:00
|
|
|
return cpu_list;
|
|
|
|
}
|
2012-08-10 18:04:15 +02:00
|
|
|
|
2013-06-21 19:09:18 +02:00
|
|
|
static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
|
|
|
|
cpu->env.nip = value;
|
|
|
|
}
|
|
|
|
|
2013-08-25 18:53:55 +02:00
|
|
|
static bool ppc_cpu_has_work(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
|
|
|
|
}
|
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
static void ppc_cpu_reset(DeviceState *dev)
|
2012-04-06 14:39:03 +02:00
|
|
|
{
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
CPUState *s = CPU(dev);
|
2012-04-06 14:39:03 +02:00
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(s);
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
2012-04-06 15:35:34 +02:00
|
|
|
target_ulong msr;
|
2014-03-19 14:03:57 +01:00
|
|
|
int i;
|
2012-04-06 15:35:34 +02:00
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
pcc->parent_reset(dev);
|
2012-04-06 14:39:03 +02:00
|
|
|
|
2012-04-06 15:35:34 +02:00
|
|
|
msr = (target_ulong)0;
|
2016-06-03 14:11:19 +02:00
|
|
|
msr |= (target_ulong)MSR_HVB;
|
2012-04-06 15:35:34 +02:00
|
|
|
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
|
|
|
|
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
|
|
|
|
msr |= (target_ulong)1 << MSR_EP;
|
|
|
|
#if defined(DO_SINGLE_STEP) && 0
|
|
|
|
/* Single step trace mode */
|
|
|
|
msr |= (target_ulong)1 << MSR_SE;
|
|
|
|
msr |= (target_ulong)1 << MSR_BE;
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
|
2018-07-03 17:17:26 +02:00
|
|
|
msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
|
|
|
|
msr |= (target_ulong)1 << MSR_FE1;
|
2012-04-06 15:35:34 +02:00
|
|
|
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
|
2014-05-29 16:12:22 +02:00
|
|
|
msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
|
2012-04-06 15:35:34 +02:00
|
|
|
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
|
|
|
|
msr |= (target_ulong)1 << MSR_PR;
|
2014-06-04 14:50:59 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
|
|
|
|
#endif
|
2014-05-29 16:12:20 +02:00
|
|
|
#if !defined(TARGET_WORDS_BIGENDIAN)
|
|
|
|
msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
|
2014-06-28 18:45:27 +02:00
|
|
|
if (!((env->msr_mask >> MSR_LE) & 1)) {
|
|
|
|
fprintf(stderr, "Selected CPU does not support little-endian.\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2014-05-29 16:12:20 +02:00
|
|
|
#endif
|
2012-04-06 15:35:34 +02:00
|
|
|
#endif
|
2013-03-29 03:06:27 +01:00
|
|
|
|
2012-04-06 15:35:34 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
2020-12-09 18:35:36 +01:00
|
|
|
if (mmu_is_64bit(env->mmu_model)) {
|
2016-03-16 10:43:52 +01:00
|
|
|
msr |= (1ULL << MSR_SF);
|
2012-04-06 15:35:34 +02:00
|
|
|
}
|
|
|
|
#endif
|
2013-03-29 03:06:27 +01:00
|
|
|
|
|
|
|
hreg_store_msr(env, msr, 1);
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nip = env->hreset_vector | env->excp_prefix;
|
|
|
|
if (env->mmu_model != POWERPC_MMU_REAL) {
|
|
|
|
ppc_tlb_invalidate_all(env);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-04-06 15:35:34 +02:00
|
|
|
hreg_compute_hflags(env);
|
|
|
|
env->reserve_addr = (target_ulong)-1ULL;
|
|
|
|
/* Be sure no exception or interrupt is pending */
|
|
|
|
env->pending_interrupts = 0;
|
2013-08-26 08:31:06 +02:00
|
|
|
s->exception_index = POWERPC_EXCP_NONE;
|
2012-04-06 15:35:34 +02:00
|
|
|
env->error_code = 0;
|
ppc: Deassert the external interrupt pin in KVM on reset
When a CPU is reset, QEMU makes sure no interrupt is pending by clearing
CPUPPCstate::pending_interrupts in ppc_cpu_reset(). In the case of a
complete machine emulation, eg. a sPAPR machine, an external interrupt
request could still be pending in KVM though, eg. an IPI. It will be
eventually presented to the guest, which is supposed to acknowledge it at
the interrupt controller. If the interrupt controller is emulated in QEMU,
either XICS or XIVE, ppc_set_irq() won't deassert the external interrupt
pin in KVM since it isn't pending anymore for QEMU. When the vCPU re-enters
the guest, the interrupt request is still pending and the vCPU will try
again to acknowledge it. This causes an infinite loop and eventually hangs
the guest.
The code has been broken since the beginning. The issue wasn't hit before
because accel=kvm,kernel-irqchip=off is an awkward setup that never got
used until recently with the LC92x IBM systems (aka, Boston).
Add a ppc_irq_reset() function to do the necessary cleanup, ie. deassert
the IRQ pins of the CPU in QEMU and most importantly the external interrupt
pin for this vCPU in KVM.
Reported-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548861740.3650476.16879693165328764758.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-04 20:43:37 +01:00
|
|
|
ppc_irq_reset(cpu);
|
2012-09-25 19:12:21 +02:00
|
|
|
|
2019-08-27 04:00:13 +02:00
|
|
|
/* tininess for underflow is detected before rounding */
|
|
|
|
set_float_detect_tininess(float_tininess_before_rounding,
|
|
|
|
&env->fp_status);
|
|
|
|
|
2014-03-19 14:03:57 +01:00
|
|
|
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
|
|
|
|
ppc_spr_t *spr = &env->spr_cb[i];
|
|
|
|
|
|
|
|
if (!spr->name) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
env->spr[i] = spr->default_value;
|
|
|
|
}
|
2012-04-06 14:39:03 +02:00
|
|
|
}
|
|
|
|
|
2014-06-24 19:51:19 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2021-02-04 17:39:13 +01:00
|
|
|
|
2014-06-24 19:51:19 +02:00
|
|
|
static bool ppc_cpu_is_big_endian(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
cpu_synchronize_state(cs);
|
|
|
|
|
|
|
|
return !msr_le;
|
|
|
|
}
|
2019-07-18 05:42:11 +02:00
|
|
|
|
2021-02-04 17:39:13 +01:00
|
|
|
#ifdef CONFIG_TCG
|
2019-07-18 05:42:11 +02:00
|
|
|
static void ppc_cpu_exec_enter(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
|
|
|
|
if (cpu->vhyp) {
|
|
|
|
PPCVirtualHypervisorClass *vhc =
|
|
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
|
|
vhc->cpu_exec_enter(cpu->vhyp, cpu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ppc_cpu_exec_exit(CPUState *cs)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
|
|
|
|
if (cpu->vhyp) {
|
|
|
|
PPCVirtualHypervisorClass *vhc =
|
|
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
|
|
vhc->cpu_exec_exit(cpu->vhyp, cpu);
|
|
|
|
}
|
|
|
|
}
|
2021-02-04 17:39:13 +01:00
|
|
|
#endif /* CONFIG_TCG */
|
|
|
|
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
2014-06-24 19:51:19 +02:00
|
|
|
|
2018-03-21 05:30:13 +01:00
|
|
|
static void ppc_cpu_instance_init(Object *obj)
|
2012-04-06 15:09:01 +02:00
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(obj);
|
2013-01-06 09:31:30 +01:00
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
2012-04-06 15:09:01 +02:00
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
2019-03-28 22:26:22 +01:00
|
|
|
cpu_set_cpustate_pointers(cpu);
|
2017-08-31 08:38:46 +02:00
|
|
|
cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
|
2013-01-06 09:31:30 +01:00
|
|
|
|
2013-02-18 00:16:41 +01:00
|
|
|
env->msr_mask = pcc->msr_mask;
|
|
|
|
env->mmu_model = pcc->mmu_model;
|
|
|
|
env->excp_model = pcc->excp_model;
|
|
|
|
env->bus_model = pcc->bus_model;
|
|
|
|
env->insns_flags = pcc->insns_flags;
|
|
|
|
env->insns_flags2 = pcc->insns_flags2;
|
|
|
|
env->flags = pcc->flags;
|
|
|
|
env->bfd_mach = pcc->bfd_mach;
|
|
|
|
env->check_pow = pcc->check_pow;
|
2013-01-06 09:31:30 +01:00
|
|
|
|
2019-03-21 12:45:46 +01:00
|
|
|
/*
|
|
|
|
* Mark HV mode as supported if the CPU has an MSR_HV bit in the
|
|
|
|
* msr_mask. The mask can later be cleared by PAPR mode but the hv
|
|
|
|
* mode support will remain, thus enforcing that we cannot use
|
|
|
|
* priv. instructions in guest in PAPR mode. For 970 we currently
|
|
|
|
* simply don't set HV in msr_mask thus simulating an "Apple mode"
|
|
|
|
* 970. If we ever want to support 970 HV mode, we'll have to add
|
|
|
|
* a processor attribute of some sort.
|
2016-06-03 14:11:19 +02:00
|
|
|
*/
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
|
|
|
|
#endif
|
|
|
|
|
2018-03-23 03:07:48 +01:00
|
|
|
ppc_hash64_init(cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ppc_cpu_instance_finalize(Object *obj)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(obj);
|
|
|
|
|
|
|
|
ppc_hash64_finalize(cpu);
|
2012-04-06 15:09:01 +02:00
|
|
|
}
|
|
|
|
|
2014-07-03 16:48:55 +02:00
|
|
|
static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
|
|
|
|
{
|
|
|
|
return pcc->pvr == pvr;
|
|
|
|
}
|
|
|
|
|
2017-09-14 17:21:40 +02:00
|
|
|
static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if ((env->hflags >> MSR_LE) & 1) {
|
|
|
|
info->endian = BFD_ENDIAN_LITTLE;
|
|
|
|
}
|
|
|
|
info->mach = env->bfd_mach;
|
|
|
|
if (!env->bfd_mach) {
|
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
info->mach = bfd_mach_ppc64;
|
|
|
|
#else
|
|
|
|
info->mach = bfd_mach_ppc;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
info->disassembler_options = (char *)"any";
|
|
|
|
info->print_insn = print_insn_ppc;
|
2017-09-14 19:38:40 +02:00
|
|
|
|
|
|
|
info->cap_arch = CS_ARCH_PPC;
|
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
info->cap_mode = CS_MODE_64;
|
|
|
|
#endif
|
2017-09-14 17:21:40 +02:00
|
|
|
}
|
|
|
|
|
2016-11-21 06:29:30 +01:00
|
|
|
static Property ppc_cpu_properties[] = {
|
|
|
|
DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
|
ppc: Rework CPU compatibility testing across migration
Migrating between different CPU versions is a bit complicated for ppc.
A long time ago, we ensured identical CPU versions at either end by
checking the PVR had the same value. However, this breaks under KVM
HV, because we always have to use the host's PVR - it's not
virtualized. That would mean we couldn't migrate between hosts with
different PVRs, even if the CPUs are close enough to compatible in
practice (sometimes identical cores with different surrounding logic
have different PVRs, so this happens in practice quite often).
So, we removed the PVR check, but instead checked that several flags
indicating supported instructions matched. This turns out to be a bad
idea, because those instruction masks are not architected information, but
essentially a TCG implementation detail. So changes to qemu internal CPU
modelling can break migration - this happened between qemu-2.6 and
qemu-2.7. That was addressed by 146c11f1 "target-ppc: Allow eventual
removal of old migration mistakes".
Now, verification of CPU compatibility across a migration basically doesn't
happen. We simply ignore the PVR of the incoming migration, and hope the
cpu on the destination is close enough to work.
Now that we've cleaned up handling of processor compatibility modes
for pseries machine type, we can do better. For new machine types
(pseries-2.10+) We allow migration if:
* The source and destination PVRs are for the same type of CPU, as
determined by CPU class's pvr_match function
OR * When the source was in a compatibility mode, and the destination CPU
supports the same compatibility mode
For older machine types we retain the existing behaviour - current CAS
code will usually set a compat mode which would break backwards
migration if we made them use the new behaviour. [Fixed from an
earlier version by Greg Kurz].
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Tested-by: Andrea Bolognani <abologna@redhat.com>
2017-06-02 04:26:11 +02:00
|
|
|
DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
|
|
|
|
false),
|
2018-05-22 12:39:59 +02:00
|
|
|
DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
|
2018-03-29 09:29:38 +02:00
|
|
|
false),
|
2016-11-21 06:29:30 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2021-05-17 12:51:31 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
#include "hw/core/sysemu-cpu-ops.h"
|
|
|
|
|
|
|
|
static const struct SysemuCPUOps ppc_sysemu_ops = {
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2021-02-04 17:39:23 +01:00
|
|
|
#ifdef CONFIG_TCG
|
|
|
|
#include "hw/core/tcg-cpu-ops.h"
|
|
|
|
|
|
|
|
static struct TCGCPUOps ppc_tcg_ops = {
|
|
|
|
.initialize = ppc_translate_init,
|
|
|
|
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
|
|
|
|
.tlb_fill = ppc_cpu_tlb_fill,
|
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
.do_interrupt = ppc_cpu_do_interrupt,
|
|
|
|
.cpu_exec_enter = ppc_cpu_exec_enter,
|
|
|
|
.cpu_exec_exit = ppc_cpu_exec_exit,
|
|
|
|
.do_unaligned_access = ppc_cpu_do_unaligned_access,
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
};
|
|
|
|
#endif /* CONFIG_TCG */
|
|
|
|
|
2012-04-06 14:39:03 +02:00
|
|
|
static void ppc_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
|
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-01-16 03:55:14 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
2018-03-21 05:30:13 +01:00
|
|
|
device_class_set_parent_realize(dc, ppc_cpu_realize,
|
2018-01-14 03:04:12 +01:00
|
|
|
&pcc->parent_realize);
|
2018-03-21 05:30:13 +01:00
|
|
|
device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
|
2018-01-14 03:04:12 +01:00
|
|
|
&pcc->parent_unrealize);
|
2014-07-03 16:48:55 +02:00
|
|
|
pcc->pvr_match = ppc_pvr_match_default;
|
2014-05-19 19:59:05 +02:00
|
|
|
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, ppc_cpu_properties);
|
2012-04-06 14:39:03 +02:00
|
|
|
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
|
2013-01-21 18:26:21 +01:00
|
|
|
|
|
|
|
cc->class_by_name = ppc_cpu_class_by_name;
|
2013-08-25 18:53:55 +02:00
|
|
|
cc->has_work = ppc_cpu_has_work;
|
2013-05-27 01:33:50 +02:00
|
|
|
cc->dump_state = ppc_cpu_dump_state;
|
|
|
|
cc->dump_statistics = ppc_cpu_dump_statistics;
|
2013-06-21 19:09:18 +02:00
|
|
|
cc->set_pc = ppc_cpu_set_pc;
|
2013-06-29 04:18:45 +02:00
|
|
|
cc->gdb_read_register = ppc_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = ppc_cpu_gdb_write_register;
|
2019-04-02 12:03:41 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2013-06-29 18:55:54 +02:00
|
|
|
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
|
cpu: Rename CPUClass vmsd -> legacy_vmsd
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-17 12:51:29 +02:00
|
|
|
cc->legacy_vmsd = &vmstate_ppc_cpu;
|
2021-05-17 12:51:31 +02:00
|
|
|
cc->sysemu_ops = &ppc_sysemu_ops;
|
2013-06-29 18:55:54 +02:00
|
|
|
#endif
|
2017-02-28 14:32:17 +01:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
|
|
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
|
|
|
|
cc->write_elf32_note = ppc32_cpu_write_elf32_note;
|
|
|
|
#endif
|
2013-06-28 23:18:47 +02:00
|
|
|
|
|
|
|
cc->gdb_num_core_regs = 71;
|
2019-02-06 17:51:33 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
|
|
|
|
#endif
|
2014-06-23 15:23:08 +02:00
|
|
|
#ifdef USE_APPLE_GDB
|
|
|
|
cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
|
|
|
|
cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
|
|
|
|
cc->gdb_num_core_regs = 71 + 32;
|
|
|
|
#endif
|
|
|
|
|
2015-12-03 13:14:41 +01:00
|
|
|
cc->gdb_arch_name = ppc_gdb_arch_name;
|
2013-07-07 15:08:22 +02:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
cc->gdb_core_xml_file = "power64-core.xml";
|
|
|
|
#else
|
|
|
|
cc->gdb_core_xml_file = "power-core.xml";
|
|
|
|
#endif
|
2014-06-24 19:51:19 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
|
|
|
|
#endif
|
2017-09-14 17:21:40 +02:00
|
|
|
cc->disas_set_info = ppc_disas_set_info;
|
2019-03-21 12:45:46 +01:00
|
|
|
|
2013-10-15 18:33:37 +02:00
|
|
|
dc->fw_name = "PowerPC,UNKNOWN";
|
2021-02-04 17:39:23 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_TCG
|
|
|
|
cc->tcg_ops = &ppc_tcg_ops;
|
|
|
|
#endif /* CONFIG_TCG */
|
2012-04-06 14:39:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ppc_cpu_type_info = {
|
|
|
|
.name = TYPE_POWERPC_CPU,
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
.instance_size = sizeof(PowerPCCPU),
|
2020-09-16 02:46:36 +02:00
|
|
|
.instance_align = __alignof__(PowerPCCPU),
|
2018-03-21 05:30:13 +01:00
|
|
|
.instance_init = ppc_cpu_instance_init,
|
2018-03-23 03:07:48 +01:00
|
|
|
.instance_finalize = ppc_cpu_instance_finalize,
|
2013-01-06 09:31:30 +01:00
|
|
|
.abstract = true,
|
2012-04-06 14:39:03 +02:00
|
|
|
.class_size = sizeof(PowerPCCPUClass),
|
|
|
|
.class_init = ppc_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
2020-05-26 19:24:24 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2016-10-28 13:06:21 +02:00
|
|
|
static const TypeInfo ppc_vhyp_type_info = {
|
|
|
|
.name = TYPE_PPC_VIRTUAL_HYPERVISOR,
|
|
|
|
.parent = TYPE_INTERFACE,
|
|
|
|
.class_size = sizeof(PPCVirtualHypervisorClass),
|
|
|
|
};
|
2020-05-26 19:24:24 +02:00
|
|
|
#endif
|
2016-10-28 13:06:21 +02:00
|
|
|
|
2012-04-06 14:39:03 +02:00
|
|
|
static void ppc_cpu_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&ppc_cpu_type_info);
|
2020-05-26 19:24:24 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2016-10-28 13:06:21 +02:00
|
|
|
type_register_static(&ppc_vhyp_type_info);
|
2020-05-26 19:24:24 +02:00
|
|
|
#endif
|
2012-04-06 14:39:03 +02:00
|
|
|
}
|
|
|
|
|
2021-05-12 16:08:05 +02:00
|
|
|
void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|
|
|
{
|
|
|
|
#define RGPL 4
|
|
|
|
#define RFPL 4
|
|
|
|
|
|
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
|
|
|
|
TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
|
|
|
|
env->nip, env->lr, env->ctr, cpu_read_xer(env),
|
|
|
|
cs->cpu_index);
|
|
|
|
qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
|
|
|
|
"%08x iidx %d didx %d\n",
|
|
|
|
env->msr, env->spr[SPR_HID0], env->hflags,
|
|
|
|
cpu_mmu_index(env, true), cpu_mmu_index(env, false));
|
|
|
|
#if !defined(NO_TIMER_DUMP)
|
|
|
|
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
" DECR " TARGET_FMT_lu
|
|
|
|
#endif
|
|
|
|
"\n",
|
|
|
|
cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
, cpu_ppc_load_decr(env)
|
|
|
|
#endif
|
|
|
|
);
|
|
|
|
#endif
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if ((i & (RGPL - 1)) == 0) {
|
|
|
|
qemu_fprintf(f, "GPR%02d", i);
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
|
|
|
|
if ((i & (RGPL - 1)) == (RGPL - 1)) {
|
|
|
|
qemu_fprintf(f, "\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, "CR ");
|
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
qemu_fprintf(f, "%01x", env->crf[i]);
|
|
|
|
qemu_fprintf(f, " [");
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
char a = '-';
|
|
|
|
if (env->crf[i] & 0x08) {
|
|
|
|
a = 'L';
|
|
|
|
} else if (env->crf[i] & 0x04) {
|
|
|
|
a = 'G';
|
|
|
|
} else if (env->crf[i] & 0x02) {
|
|
|
|
a = 'E';
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
|
|
|
|
env->reserve_addr);
|
|
|
|
|
|
|
|
if (flags & CPU_DUMP_FPU) {
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if ((i & (RFPL - 1)) == 0) {
|
|
|
|
qemu_fprintf(f, "FPR%02d", i);
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
|
|
|
|
if ((i & (RFPL - 1)) == (RFPL - 1)) {
|
|
|
|
qemu_fprintf(f, "\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
|
|
|
|
" PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_SRR0], env->spr[SPR_SRR1],
|
|
|
|
env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
|
|
|
|
" SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
|
|
|
|
env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
|
|
|
|
" SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
|
|
|
|
env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
if (env->excp_model == POWERPC_EXCP_POWER7 ||
|
|
|
|
env->excp_model == POWERPC_EXCP_POWER8 ||
|
|
|
|
env->excp_model == POWERPC_EXCP_POWER9 ||
|
|
|
|
env->excp_model == POWERPC_EXCP_POWER10) {
|
|
|
|
qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
if (env->excp_model == POWERPC_EXCP_BOOKE) {
|
|
|
|
qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
|
|
|
|
" MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
|
|
|
|
env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
|
|
|
|
" ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
|
|
|
|
env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
|
|
|
|
" IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
|
|
|
|
env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
|
|
|
|
" EPR " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
|
|
|
|
env->spr[SPR_BOOKE_EPR]);
|
|
|
|
|
|
|
|
/* FSL-specific */
|
|
|
|
qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
|
|
|
|
" PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
|
|
|
|
env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IVORs are left out as they are large and do not change often --
|
|
|
|
* they can be read with "p $ivor0", "p $ivor1", etc.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
if (env->flags & POWERPC_FLAG_CFAR) {
|
|
|
|
qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (env->spr_cb[SPR_LPCR].name) {
|
|
|
|
qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (env->mmu_model) {
|
|
|
|
case POWERPC_MMU_32B:
|
|
|
|
case POWERPC_MMU_601:
|
|
|
|
case POWERPC_MMU_SOFT_6xx:
|
|
|
|
case POWERPC_MMU_SOFT_74xx:
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
case POWERPC_MMU_64B:
|
|
|
|
case POWERPC_MMU_2_03:
|
|
|
|
case POWERPC_MMU_2_06:
|
|
|
|
case POWERPC_MMU_2_07:
|
|
|
|
case POWERPC_MMU_3_00:
|
|
|
|
#endif
|
|
|
|
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
|
|
|
|
qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
|
|
|
|
}
|
|
|
|
if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
|
|
|
|
qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
|
|
|
|
}
|
|
|
|
qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_DAR], env->spr[SPR_DSISR]);
|
|
|
|
break;
|
|
|
|
case POWERPC_MMU_BOOKE206:
|
|
|
|
qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
|
|
|
|
" MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
|
|
|
|
env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
|
|
|
|
" MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
|
|
|
|
env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
|
|
|
|
|
|
|
|
qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
|
|
|
|
" TLB1CFG " TARGET_FMT_lx "\n",
|
|
|
|
env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
|
|
|
|
env->spr[SPR_BOOKE_TLB1CFG]);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#undef RGPL
|
|
|
|
#undef RFPL
|
|
|
|
}
|
2012-04-06 14:39:03 +02:00
|
|
|
type_init(ppc_cpu_register_types)
|